MAX1490EBCPG+ Maxim Integrated Products, MAX1490EBCPG+ Datasheet - Page 15

• Manufacturer Part Number: MAX1490EBCPG+
• Description: IC RS485/RS422 DATA INTRFC 24DIP
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of MAX1490EBCPG+

• Number Of Drivers/receivers: 1/1
• Protocol: RS422, RS485
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.600", 15.24mm)
• Data Rate: 250 Kbps
• Operating Supply Voltage: 5 V
• Supply Current: 130 mA
• Operating Temperature Range: 0 C to + 70 C
• Maximum Power Dissipation: 696 mW
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

___________Applications Information
These E versions of the MAX1480EA/MAX1480EC/
1490EA/MAX1490EB provide extra protection against
ESD. The rugged MAX1480EA/MAX1480EC/MAX1490EA/
MAX1490EB are intended for harsh environments where
high-speed communication is important. These devices
eliminate the need for transient suppressor diodes or the
use of discrete protection components. The standard
(non-E) MAX1480A/MAX1480C/MAX1490A/MAX1490B
are recommended for applications where cost is critical.
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The driver outputs and receiver inputs have extra protec-
tion against static electricity. Maxim’s engineers devel-
oped state-of-the-art structures to protect these pins
against ESD of ±15kV without damage. The ESD struc-
tures withstand high ESD in all states: normal operation,
shutdown, and powered down. After an ESD event,
Maxim’s MAX1480EA/MAX1480EC/MAX1490EA/
MAX1490EB keep working without latchup. An isolation
capacitor of 270pF 4kV should be placed between ISO
COM and logic ground for optional performance against
an ESD pulse with respect to logic ground.
ESD protection can be tested in various ways; the trans-
mitter outputs and receiver inputs of this product family
are characterized for protection to ±15kV using the
Human Body Model.
The ±15kV ESD test specifications apply only to the A, B,
Y, and Z I/O pins. The test surge may be referenced to
either the ISO COM or to the nonisolated GND (Figures 1
and 2).
Figure 13. Human Body ESD Test Model
VOLTAGE
SOURCE
±15kV ESD-Protected, Isolated RS-485/RS-422
HIGH-
DC
CHARGE-CURRENT
LIMIT RESISTOR
R
C
100pF
1MΩ
______________________________________________________________________________________
C s
STORAGE
CAPACITOR
R
RESISTANCE
DISCHARGE
D
±15kV ESD Protection
1500Ω
ESD Test Conditions
DEVICE
UNDER
TEST
Figure 13 shows the Human Body Model, and Figure 14
shows the current waveform it generates when dis-
charged into low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kΩ resistor.
The Machine Model for ESD tests all pins using a 200pF
storage capacitor and zero discharge resistance. Its
objective is to simulate the stress caused by contact that
occurs with handling and assembly during manufactur-
ing. All pins require this protection during manufactur-
ing—not just inputs and outputs. Therefore, after PC
board assembly, the Machine Model is less relevant to
I/O ports.
The MAX1480EA/MAX1480EC are designed for bidirec-
tional data communications on multipoint bus-transmis-
sion lines. The MAX1490EA/MAX1490EB are designed
for full-duplex bidirectional communications that are pri-
marily point-to-point. Figures 15 and 16 show half-duplex
and full-duplex typical network application circuits,
respectively. To minimize reflections, terminate the line at
both ends with its characteristic impedance, and keep
stub lengths off the main line as short as possible. The
slew-rate-limited MAX1480EC/MAX1490EB are more tol-
erant of imperfect termination and stubs off the main line.
The MAX1480EA/MAX1480EC/MAX1490EA/MAX1490EB
pinouts enable optimal PC board layout by minimizing
interconnect lengths and crossovers:
• For maximum isolation, the “isolation barrier” should
Figure 14. Human Body Current Waveform
AMPERES
not be breached except by the MAX1480EA/
I
P
36.8%
100%
90%
10%
0
0
t
RL
Data Interfaces
CURRENT WAVEFORM
TIME
Layout Considerations
t
DL
I r
Human Body Model
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
Machine Model
15