PIC16F819-I/SS Microchip Technology Inc., PIC16F819-I/SS Datasheet - Page 78

• Manufacturer Part Number: PIC16F819-I/SS
• Description: 20 PIN, 3.5 KB FLASH, 256 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F819-I/SS

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 20-pin SSOP
• Programmable Memory: 3.5K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F818/819
10.3
The SSP module in I
functions, except general call support and provides
interrupts on Start and Stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RB4/SCK/SCL pin, which is the clock (SCL) and the
RB1/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISB<4,1> bits.
EXAMPLE 10-1:
The SSP module functions are enabled by setting SSP
Enable bit, SSPEN (SSPCON<5>).
FIGURE 10-5:
The SSP module has five registers for I
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) – Not directly
• SSP Address Register (SSPADD)
DS39598E-page 76
RB4/SCK/
MOVF
IORLW
ANDLW
MOVWF
accessible
RB1/
SDI/
SDA
SCL
module
SSP I
TRISC, W
0x18
B’11111001’
TRISC
Read
2
Clock
Shift
implements
C Mode Operation
2
MSb
C mode fully implements all slave
SSP BLOCK DIAGRAM
(I
Stop Bit Detect
SSPBUF Reg
SSPADD Reg
Match Detect
2
SSPSR Reg
Start and
C™ MODE)
; Example for an 18-pin part such as the PIC16F818/819
; Ensures <4:3> bits are ‘11’
; Sets <2:1> as output, but will not alter other bits
; User can use their own logic here, such as IORLW, XORLW and ANDLW
the
LSb
Write
standard
(SSPSTAT Reg)
2
Data Bus
C operation:
Internal
Addr Match
Set, Reset
S, P Bits
mode
To ensure proper communication of the I
the TRIS bits (TRISx [SDA, SCL]) corresponding to the
I
of the port containing the I
are changed in software during I
using a Read-Modify-Write instruction (BSF, BCF), then
the I
communication may suspend. Do not change any of the
TRISx bits (TRIS bits of the port containing the I
using the instruction BSF or BCF during I
tion. If it is absolutely necessary to change the TRISx
bits during communication, the following method can be
used:
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed to inputs by
setting the appropriate TRISB bits. Pull-up resistors
must be provided externally to the SCL and SDA pins
for proper operation of the I
Additional information on SSP I
found in the “PICmicro
Reference Manual” (DS33023).
2
C pins must be set to ‘1’. If any TRIS bits (TRISx<7:0>)
Stop bit interrupts enabled to support Firmware
Master mode
Stop bit interrupts enabled to support Firmware
Master mode
and Stop bit interrupts enabled, slave is Idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address) with Start and
C Slave mode (10-bit address) with Start and
C Firmware Controlled Master mode with Start
2
C mode may stop functioning properly and I
2
C mode, with the SSPEN bit set,
2
C modes to be selected:
 2004 Microchip Technology Inc.
®
2
C pins (PORTx [SDA, SCL])
2
Mid-Range MCU Family
C module.
2
C operation may be
2
C communication
2
2
C Slave mode,
C communica-
2
C opera-
2
C pins)
2
C