PIC16C770/P Microchip Technology Inc., PIC16C770/P Datasheet - Page 74
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC16C770/P
Manufacturer Part Number
PIC16C770/P
Description
20 PIN, 3.5 KB OTP, 256 RAM, 16 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16C770P.pdf
(220 pages)
Specifications of PIC16C770/P
A/d Inputs
6-Channel, 12-Bit
Cpu Speed
5 MIPS
Eeprom Memory
0 Bytes
Input Output
16
Interface
I2C/SPI
Memory Type
OTP
Number Of Bits
8
Package Type
20-pin PDIP
Programmable Memory
3.5K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.5-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16C717/770/771
9.1.4
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 9-2) is to broad-
cast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI
module is only going to receive, the SDO output could
be disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “line activity monitor”.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
FIGURE 9-3:
DS41120B-page 72
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
SDO
(CKE = 1)
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
MASTER MODE
SPI MODE WAVEFORM (MASTER MODE)
bit7
bit7
bit7
bit7
bit6
bit6
Advance Information
bit5
bit5
bit4
bit4
Figure 9-3, Figure 9-5 and Figure 9-6, where the MSb
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the follow-
ing:
• F
• F
• F
• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 8.25 MHz.
Figure 9-3 shows the waveforms for Master mode.
When CKE = 1, the SDO data is valid before there is a
clock edge on SCK. The change of the input sample is
shown based on the state of the SMP bit. The time
when the SSPBUF is loaded with the received data is
shown.
bit3
bit3
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit2
bit2
CY
)
bit1
bit1
CY
CY
)
)
2002 Microchip Technology Inc.
bit0
bit0
bit0
bit0
Next Q4 cycle
after Q2
4 Clock
modes
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