PIC16F73-I/SO Microchip Technology Inc., PIC16F73-I/SO Datasheet - Page 82

• Manufacturer Part Number: PIC16F73-I/SO
• Description: 28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F73-I/SO

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X
TABLE 10-8:
10.4
Synchronous Slave mode differs from the Master
mode, in that the shift clock is supplied externally at the
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
10.4.1
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
DS30325B-page 80
Address
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
The first word will immediately transfer to the
TSR register and transmit when the master
device drives the CK line.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
USART Synchronous Slave Mode
USART SYNCHRONOUS SLAVE
TRANSMIT
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
Name
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
CSRC
SPEN
Bit 7
GIE
(1)
(1)
PEIE
ADIF
ADIE
Bit 6
RX9
TX9
TMR0IE
SREN
TXEN
RCIE
RCIF
Bit 5
CREN
SYNC
INTE
TXIE
Bit 4
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
RBIE
Bit 3
—
—
Follow these steps when setting up a Synchronous
Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
TMR0IF
BRGH
FERR
Bit 2
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
If using interrupts, ensure that GIE and PEIE in
the INTCON register are set.
OERR
TRMT
Bit 1
INTF
RX9D
TX9D
RBIF
Bit 0
 2002 Microchip Technology Inc.
0000 000x
0000 -00x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on:
0000 000u
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
RESETS
all other