PIC16F73-I/SO Microchip Technology Inc., PIC16F73-I/SO Datasheet - Page 53

• Manufacturer Part Number: PIC16F73-I/SO
• Description: 28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F73-I/SO

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.0
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device RESET.
The input clock (F
1:4
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Register 7-1 shows the Timer2 control register.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
 2002 Microchip Technology Inc.
or
TIMER2 MODULE
1:16,
OSC
selected
/4) has a prescale option of 1:1,
by
control
bits
7.1
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, MCLR Reset, WDT
TMR2 is not cleared when T2CON is written.
7.2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
FIGURE 7-1:
Reset or BOR)
Note 1: TMR2 register output can be software selected by the
Sets Flag
bit TMR2IF
T2OUTPS3:
1:1 to 1:16
T2OUTPS0
Postscaler
Timer2 Prescaler and Postscaler
Output of TMR2
SSP module as a baud clock.
4
TMR2
Output
Reset
EQ
(1)
Comparator
TMR2 reg
TIMER2 BLOCK DIAGRAM
PR2 reg
PIC16F7X
1:1, 1:4, 1:16
Prescaler
DS30325B-page 51
T2CKPS1:
T2CKPS0
2
F
OSC
/4