DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 18

• Manufacturer Part Number: DS3251+
• Description: IC LIU DS3/E3/STS-1 144-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS3251+

• Number Of Drivers/receivers: 1/1
• Protocol: DS3
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 144-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit
Name
Default
Bit 7: ITU CV Mode (ITU). This bit controls what types of bipolar violations (BPVs) are flagged as code violations
on the RLCV pin and counted in the
flagged and counted. An EXZ event is the occurrence of a third consecutive zero (DS3 or STS-1 modes) or fourth
consecutive zero (E3 mode) in a sequence of zeros.
Bit 6: Receiver Binary Interface Enable (RBIN)
Bit 5: Receiver Clock Invert (RCINV)
Bit 4: Receiver Jitter Attenuator Enable (RJA). (Note that TCR:TJA = 1 takes precedence over RJA = 1.)
Bit 3: Receiver Power-Down Enable (RPD)
Bit 2: Receiver Tri-State Enable (RTS). This signal is set to 1 on reset, which tri-states the receiver RPOS/RDAT,
RNEG/RLCV, and RCLK pins. The receiver is left powered up in this mode. The RTS pin is inverted and logically
ORed with this bit.
Bit 1: Receiver Monitor Preamp Enable (RMON)
Bit 0: Receive Code-Violation Counter Update (RCVUD). When this control bit transitions from low to high, the
RCVL
is cleared.
and
0 = In all three modes (DS3, E3, and STS-1) BPVs that are not part of a valid codeword are flagged and
1 = In DS3 and STS-1 modes, BPVs that are not part of valid codewords are flagged and counted. In E3
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code violations.
0 = RPOS/RDAT and RNEG/RLCV are sampled on the falling edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV are sampled on the rising edge of RCLK.
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
0 = enable the receiver
1 = power-down the receiver (RPOS/RDAT, RNEG/RLCV, and RCLK tri-stated)
0 = enable the receiver outputs
1 = tri-state the receiver outputs (RPOS/RDAT, RNEG/RLCV, and RCLK)
0 = disable the monitor preamp
1 = enable the monitor preamp
0→1 = Update
RCVH
counted. EXZ events are also flagged and counted.
mode, BPVs that are the same polarity as the last BPV are flagged and counted. EXZ events are not
flagged and counted in any mode.
disabled.
The B3ZS/HDB3 encoder is enabled.
ITU
registers are loaded with the current code-violation count, and the internal code-violation counter
7
0
RCV
registers and clear internal code-violation counter
RBIN
6
0
RCRn
Receiver Configuration Register
02h, 12h, 22h, 32h
RCV
RCINV
register. It also controls whether or not excessive zero (EXZ) events are
5
0
18 of 71
RJA
4
0
RPD
0
3
RTS
2
1
RMON
1
0
RCVUD
0
0