DS3251+ Maxim Integrated Products, DS3251+ Datasheet - Page 46

IC LIU DS3/E3/STS-1 144-CSBGA

DS3251+

Manufacturer Part Number
DS3251+
Description
IC LIU DS3/E3/STS-1 144-CSBGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheets

Specifications of DS3251+

Number Of Drivers/receivers
1/1
Protocol
DS3
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
144-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 8-11. SPI Bus Transactions
8.10 Interrupt Structure
The interrupt structure is designed to efficiently guide the user to the source of an interrupt. The status bits in the
global interrupt status register (GLOBAL.ISR) are read to determine if the interrupt source comes from a global
event, such as a one-second timer interrupt, or one of the ports. If the interrupt source is a global event, the global
status register is read (GLOBAL.SRL) to determine the source. If the interrupt source is a port, the port interrupt
status register (PORT.ISR) is read to determine if the interrupt source comes from a port event, such as a
performance monitor update interrupt, or one of the functional blocks inside the port. If the interrupt source is a port
event, the port status register is read (PORT.SRL) to determine the source. If the interrupt source is from a
functional block inside the port, the associated block's status register is read to determine the source. The source
of an interrupt can be determined by reading no more than three 16-bit registers.
Once the interrupt source has been determined, the interrupt can be cleared by either reading or writing the latched
status register (see Section 8.8.5). An alternate method for clearing an interrupt is to disable the interrupt at the bit,
block, port, or global level by writing a zero to the associated interrupt enable bit. Note: Disabling the interrupt at
the block, port, or global level disables all interrupts sources at or below that level.
SDO
SDO
SDO
SDO
Single-Byte Write
Single-Byte Read
Burst Write
Burst Read
SDI
SDI
SDI
SDI
CS
CS
CS
CS
R/W Register Address Burst
R/W Register Address Burst
R/W Register Address Burst Data Byte 1
R/W Register Address Burst
0 (Write)
1 (Read)
0 (Write)
1 (Read)
0 (single-byte)
0 (single-byte)
1 (burst)
1 (burst)
Data Byte 1
Data Byte
Data Byte
46 of 130
Data Byte N
Data Byte N
DS32506/DS32508/DS32512

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