DSPIC30F6010A-30I/PT Microchip Technology Inc., DSPIC30F6010A-30I/PT Datasheet - Page 26

• Manufacturer Part Number: DSPIC30F6010A-30I/PT
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6010A-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

dsPIC30F
6.
FIGURE 2-7:
7.
FIGURE 2-8:
8.
DS70082G-page 24
1. PUSH DOEND
2. DO LABEL,#COUNT
2a.Second Word
3. 1st Instruction of Loop
1. MOV.b W0,[W1]
2. MOV.b [W1],PORTB
2a.Stall (NOP)
3. MOV.b W0,PORTB
Two-word instructions for DO. In these instruc-
tions, the fetch after the instruction contains an
address offset. This address offset is added to
the first instruction address to generate the last
loop instruction address. Therefore, these
instructions require 2 cycles, as shown in
Figure 2-7.
Instructions that are subjected to a stall due to a
data dependency between the X RAGU and X
WAGU. An additional cycle is inserted to resolve
the resource conflict, as shown in Figure 2-8.
Instruction stalls caused by data dependencies
are further discussed in Section 4.0.
Interrupt
Section 5.0 for details on interrupts.
recognition
INSTRUCTION PIPELINE FLOW: 2-WORD, 2-CYCLE DO, DOW
INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE WITH INSTRUCTION STALL
Fetch 1
T
Fetch 1
execution.
CY
T
0
CY
0
Execute 1
Fetch 2L
T
Execute 1
Fetch 2
Refer
CY
T
1
CY
1
to
Preliminary
NOP
Fetch 2H
T
NOP
Stall
CY
T
2
CY
2
Execute 2
Execute 2
Fetch 3
T
Fetch 3
CY
T
3
CY
3
Execute 3
T
Execute 3
CY
4
T
 2004 Microchip Technology Inc.
CY
4
T
CY
5