DSPIC30F6010A-30I/PT Microchip Technology Inc., DSPIC30F6010A-30I/PT Datasheet - Page 24

• Manufacturer Part Number: DSPIC30F6010A-30I/PT
• Description: 16 BIT MCU/DSP 80LD 30MIPS 144 KB FLASH
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F6010A-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 68
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 68
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 80-pin TQFP
• Programmable Memory: 144K Bytes
• Ram Size: 8K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part

dsPIC30F
2.3
There are 8 types of instruction flows:
1.
FIGURE 2-2:
2.
FIGURE 2-3:
DS70082G-page 22
1. MOV.b #0x55,W0
2. MOV.b #0x35,W1
3. ADD.b W0,W1,W2
1. MOV #0x55,W0
2. BTSC W1,#3
3. ADD W0,W1,W2
4. BRA SUB_1
5. SUB W0,W1,W3
6. Instruction @ address SUB_1
Normal one-word, one-cycle instructions: these
instructions take one effective cycle to execute,
as shown in Figure 2-2.
One-word, two-cycle (or three-cycle) instruc-
tions that are flow control instructions: these
instructions include the relative branches, rela-
tive call, skips and returns. When an instruction
changes the PC (other than to increment it), the
pipeline fetch is discarded. This causes the
instruction to take two effective cycles to exe-
cute as shown in Figure 2-3. Some instructions
that change program flow require 3 cycles, such
as the RETURN, RETFIE and RETLW instruc-
tions, and instructions that skip over 2-word
instructions.
Instruction Flow
INSTRUCTION PIPELINE FLOW: 1-WORD, 1-CYCLE
INSTRUCTION PIPELINE FLOW: 1-WORD, 2-CYCLE
Fetch 1
Fetch 1
T
T
CY
CY
0
0
Execute 1
Fetch 2
Execute 1
Fetch 2
T
T
CY
CY
1
1
Preliminary
Execute 2
Fetch 3
Execute 2
Skip Taken
Fetch 3
T
T
CY
CY
2
2
Execute 3
Flush
Fetch 4
T
T
CY
CY
3
3
Execute 4
Fetch 5
T
T
 2004 Microchip Technology Inc.
CY
CY
4
4
Flush
Fetch SUB_1
T
T
CY
CY
5
5