PIC16F818-I/SO Microchip Technology Inc., PIC16F818-I/SO Datasheet - Page 68

• Manufacturer Part Number: PIC16F818-I/SO
• Description: 18 PIN, 1.75 KB FLASH, 128 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F818-I/SO

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F818/819
9.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on the CCP1 pin. An event is defined as:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
9.1.1
In Capture mode, the CCP1 pin should be configured
as an input by setting the TRISB<x> bit.
FIGURE 9-1:
DS39598E-page 66
CCP1 pin
Note 1: If the CCP1 pin is configured as an
2: The TRISB bit (2 or 3) is dependent upon
Capture Mode
Edge Detect
Q’s
CCP PIN CONFIGURATION
Prescaler
output, a write to the port can cause a
capture condition.
the setting of configuration bit 12
(CCPMX).
1, 4, 16
and
CCP1CON<3:0>
Set Flag bit CCP1IF
(PIR1<2>)
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L
9.1.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
9.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit,
CCP1IE (PIE1<2>), clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in operating mode.
9.1.4
There are four prescaler settings specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
EXAMPLE 9-1:
CLRF
MOVLW
MOVWF
non-zero
CCP1CON
NEW_CAPT_PS ;Load the W reg with
CCP1CON
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
CCP PRESCALER
prescaler.
CHANGING BETWEEN
CAPTURE PRESCALERS
;Turn CCP module off
;the new prescaler
;move value and CCP ON
;Load CCP1CON with this
;value
 2004 Microchip Technology Inc.
Example 9-1
shows
the