PIC16F818-I/SO Microchip Technology Inc., PIC16F818-I/SO Datasheet - Page 27

• Manufacturer Part Number: PIC16F818-I/SO
• Description: 18 PIN, 1.75 KB FLASH, 128 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F818-I/SO

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 1.75K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.0
The data EEPROM and Flash program memory are
readable and writable during normal operation (over
the full V
in the register file space. Instead, it is indirectly
addressed through the Special Function Registers.
There are six SFRs used to read and write this
memory:
• EECON1
• EECON2
• EEDATA
• EEDATH
• EEADR
• EEADRH
This section focuses on reading and writing data
EEPROM and Flash program memory during normal
operation. Refer to the appropriate device program-
ming specification document for serial programming
information.
When interfacing the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 128 or 256 bytes of data
EEPROM, with an address range from 00h to 0FFh.
Addresses from 80h to FFh are unimplemented on the
PIC16F818 device and will read 00h. When writing to
unimplemented locations, the charge pump will be
turned off.
When interfacing the program memory block, the
EEDATA and EEDATH registers form a two-byte word
that holds the 14-bit data for read/write and the EEADR
and EEADRH registers form a two-byte word that holds
the 13-bit address of the EEPROM location being
accessed. These devices have 1K or 2K words of
program Flash, with an address range from 0000h to
03FFh for the PIC16F818 and 0000h to 07FFh for the
PIC16F819. Addresses above the range of the respec-
tive device will wraparound to the beginning of program
memory.
The EEPROM data memory allows single byte read
and write. The Flash program memory allows single-
word reads and four-word block writes. Program
memory writes must first start with a 32-word block
erase, then write in 4-word blocks. A byte write in data
EEPROM memory automatically erases the location
and writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
 2004 Microchip Technology Inc.
DD
DATA EEPROM AND FLASH
PROGRAM MEMORY
range). This memory is not directly mapped
When the device is code-protected, the CPU may
continue to read and write the data EEPROM memory.
Depending on the settings of the write-protect bits, the
device may or may not be able to write certain blocks
of the program memory; however, reads of the program
memory are allowed. When code-protected, the device
programmer can no longer access data or program
memory; this does NOT inhibit internal reads or writes.
3.1
The EEADRH:EEADR register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 8K words of program EEPROM. When
selecting a data address value, only the LSB of the
address is written to the EEADR register. When select-
ing a program address value, the MSB of the address
is written to the EEADRH register and the LSB is
written to the EEADR register.
If the device contains less memory than the full address
reach of the address register pair, the Most Significant
bits of the registers are not implemented. For example,
if the device has 128 bytes of data EEPROM, the Most
Significant bit of EEADR is not implemented on access
to data EEPROM.
3.2
EECON1 is the control register for memory accesses.
Control bit, EEPGD, determines if the access will be a
program or data memory access. When clear, as it is
when Reset, any subsequent operations will operate
on the data memory. When set, any subsequent
operations will operate on the program memory.
Control bits, RD and WR, initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write or erase
operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is
interrupted by a MCLR or a WDT Time-out Reset
during normal operation. In these situations, following
Reset, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDATA and EEADR registers.
Interrupt flag bit, EEIF in the PIR2 register, is set when
the write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the EEPROM write sequence.
EEADR and EEADRH
EECON1 and EECON2 Registers
PIC16F818/819
DS39598E-page 25