PIC18F442-I/PT Microchip Technology Inc., PIC18F442-I/PT Datasheet - Page 51

• Manufacturer Part Number: PIC18F442-I/PT
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-TQFP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F442-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

4.10
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the ’a’ bit (for
access bit).
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers, so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
FIGURE 4-8:
© 2006 Microchip Technology Inc.
Note 1: For register file map detail, see Table 4-1.
Bank Select
Access Bank
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
registers of the Access Bank.
BSR<3:0>
(2)
DIRECT ADDRESSING
Location Select
7
Data
Memory
From Opcode
(1)
(3)
Direct Addressing
(3)
000h
0FFh
Bank 0
00h
4.11
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
0
100h
1FFh
Bank 1
01h
Bank Select Register (BSR)
PIC18FXX2
E00h
EFFh
Bank 14
0Eh
DS39564C-page 49
F00h
FFFh
Bank 15
0Fh