PIC18F442-I/PT Microchip Technology Inc., PIC18F442-I/PT Datasheet - Page 26

• Manufacturer Part Number: PIC18F442-I/PT
• Description: Microcontroller; 16 KB Flash; 768 RAM; 256 EEPROM; 36 I/O; 40-Pin-TQFP
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F442-I/PT

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin TQFP
• Programmable Memory: 16K Bytes
• Ram Size: 768 Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

PIC18FXX2
2.7
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor
TABLE 2-3:
2.8
Power up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET, until the device power supply and clock are
stable. For additional information on RESET operation,
see Section 3.0.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
DS39564C-page 24
Note:
Effects of SLEEP Mode on the
On-Chip Oscillator
Power-up Delays
LP, XT, and HS
See Table 3-1, in the “Reset” section, for time-outs due to SLEEP and MCLR Reset.
OSC Mode
RCIO
ECIO
RC
EC
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Feedback inverter disabled, at
Floating, external resistor
Floating, external resistor
quiescent voltage level
should pull high
should pull high
OSC1 Pin
Floating
Floating
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
With the PLL enabled (HS/PLL Oscillator mode), the
time-out sequence following a Power-on Reset is differ-
ent from other Oscillator modes. The time-out
sequence is as follows: First, the PWRT time-out is
invoked after a POR time delay has expired. Then, the
Oscillator Start-up Timer (OST) is invoked. However,
this is still not a sufficient amount of time to allow the
PLL to lock at high frequencies. The PWRT timer is
used to provide an additional fixed 2 ms (nominal)
time-out to allow the PLL ample time to lock to the
incoming clock frequency.
Feedback inverter disabled, at
Configured as PORTA, bit 6
Configured as PORTA, bit 6
quiescent voltage level
© 2006 Microchip Technology Inc.
At logic low
At logic low
OSC2 Pin