PIC18F252-I/SP Microchip Technology Inc., PIC18F252-I/SP Datasheet - Page 93
PIC18F252-I/SP
Manufacturer Part Number
PIC18F252-I/SP
Description
Microcontroller; 32 KB Flash; 1536 RAM; 256 EEPROM; 25 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F252-ISP.pdf
(332 pages)
Specifications of PIC18F252-I/SP
A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC18F252-I/SP
Manufacturer:
PANASONIC
Quantity:
35 000
Company:
Part Number:
PIC18F252-I/SP
Manufacturer:
MICP0CRIP
Quantity:
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PIC18F252-I/SP
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Quantity:
20 000
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FIGURE 9-5:
FIGURE 9-6:
© 2006 Microchip Technology Inc.
Note 1:
Note 1:
2:
2:
3:
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
CCP Output
CCP2 Input
I/O pin has diode protection to V
To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register.
RD PORTB
Enable
CCP Output
WR LATB or
WR PORTB
WR TRISB
RBPU
Data Bus
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3 PIN
(3)
(2)
CCP2MX
(3)
(3)
Data Bus
WR TRIS
WR Port
RB0/INT
RBPU
(2)
Schmitt Trigger
Buffer
RD TRISB
RD PORTB
RD LATB
TRIS Latch
Data Latch
D
D
CK
CK
DD
DD
and V
Q
Q
and V
RD TRIS
RD Port
TRIS Latch
Data Latch
CCP2MX = 0
D
D
CK
CK
SS
SS
.
Schmitt Trigger
Buffer
.
Q
Q
Q
1
0
EN
D
Q
EN
TTL
Input
Buffer
D
V
P
RD Port
DD
Weak
Pull-up
V
I/O pin
V
N
P
SS
DD
(1)
TTL
Input
Buffer
V
P
DD
Weak
Pull-up
PIC18FXX2
I/O pin
(1)
DS39564C-page 91
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