PIC16F73-I/SP Microchip Technology Inc., PIC16F73-I/SP Datasheet - Page 20

• Manufacturer Part Number: PIC16F73-I/SP
• Description: 28 PIN, 7 KB FLASH, 192 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F73-I/SP

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 192 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F7X
TABLE 2-1:
DS30325B-page 18
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
Legend:
Note
Address
Bank 2
Bank 3
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(1,4)
(4)
(1,4)
(4)
1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
INDF
TMR0
PCL
STATUS
FSR
—
PORTB
—
—
—
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
INDF
OPTION_REG
PCL
STATUS
FSR
—
TRISB
—
—
—
PCLATH
INTCON
PMCON1
—
—
—
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter during branches ( CALL or GOTO ).
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Latch when written: PORTB pins when read
Unimplemented
Unimplemented
Unimplemented
Data Register Low Byte
Address Register Low Byte
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
PORTB Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Reserved maintain clear
Reserved maintain clear
RBPU
—
Bit 7
GIE
GIE
IRP
IRP
—
—
—
—
(6)
INTEDG
Bit 6
PEIE
PEIE
RP1
RP1
—
—
—
—
—
Data Register High Byte
TMR0IE
TMR0IE
T0CS
Bit 5
RP0
RP0
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
Address Register High Byte
Write Buffer for the upper 5 bits of the Program Counter
T0SE
INTE
INTE
Bit 4
TO
TO
—
RBIE
RBIE
Bit 3
PSA
PD
PD
—
TMR0IF
TMR0IF
Bit 2
PS2
—
Z
Z
INTF
INTF
Bit 1
PS1
DC
DC
—
 2002 Microchip Technology Inc.
Bit 0
RBIF
RBIF
PS0
RD
C
C
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx xxxx
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
1111 1111 20, 44, 96
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
---0 0000
0000 000x
1--- ---0
0000 0000
0000 0000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
on page
Details
27, 96
45, 96
26, 96
19, 96
27, 96
34, 96
21, 96
23, 96
29, 97
29, 97
29, 97
29, 97
27, 96
26, 96
19, 96
27, 96
34, 96
21, 96
23, 96
29, 97
—
—
—
—
—
—
—
—