PIC24FJ32GA002-I/SP Microchip Technology Inc., PIC24FJ32GA002-I/SP Datasheet - Page 209
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PIC24FJ32GA002-I/SP
Manufacturer Part Number
PIC24FJ32GA002-I/SP
Description
MCU, 16-Bit, 28-Pin, 32KB Flash, 8KB RAM, 21 I/O, Nanowatt
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24FJ32GA002-ISP.pdf
(256 pages)
Specifications of PIC24FJ32GA002-I/SP
A/d Inputs
10 Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Memory Capacity
32 Kbytes
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
21
Number Of Pins
28
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
8K Bytes
Speed
32 MHz
Timers
5-16-bit
Voltage, Range
2-3.6 V
Voltage, Rating
2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ32GA002-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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23.2
All of the PIC24FJ64GA004 family of devices power
their core digital logic at a nominal 2.5V. This may
create an issue for designs that are required to operate
at a higher typical voltage, such as 3.3V. To simplify
system design, all devices in the PIC24FJ64GA family
incorporate an on-chip regulator that allows the device
to run its core logic from V
The regulator is controlled by the DISVREG pin. Tying
V
vides power to the core from the other V
the regulator is enabled, a low-ESR capacitor (such as
ceramic) must be connected to the V
(Figure 23-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor
is provided in Section 26.1 “DC Characteristics”.
If DISVREG is tied to V
this case, separate power for the core logic at a nomi-
nal 2.5V must be supplied to the device on the
V
levels, typically 3.3V. Alternatively, the V
and V
nominal voltage. Refer to Figure 23-1 for possible
configurations.
23.2.1
When it is enabled, the on-chip regulator provides a
constant voltage of 2.5V nominal to the digital core
logic.
The regulator can provide this level from a V
2.5V, all the way up to the device’s V
have the capability to boost V
order to prevent “brown out” conditions when the volt-
age drops too low for the regulator, the regulator enters
Tracking mode. In Tracking mode, the regulator output
follows V
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, Low-Voltage
Detect circuit. When V
ating voltage, the circuit sets the Low-Voltage Detect
Interrupt Flag, LVDIF (PIR3<6>). This can be used to
generate an interrupt and put the application into a
low-power operational mode, or trigger an orderly
shutdown.
Low-Voltage Detection is only available when the
regulator is enabled.
© 2007 Microchip Technology Inc.
SS
DDCORE
to the pin enables the regulator, which in turn, pro-
DD
On-Chip Voltage Regulator
pins can be tied together to operate at a lower
DD
/V
CAP
, with a typical voltage drop of 100 mV.
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
pin to run the I/O pins at higher voltage
DD
DD
drops below full-speed oper-
, the regulator is disabled. In
DD
.
DD
levels below 2.5V. In
DDMAX
DDCORE
DD
DDCORE
. It does not
pins. When
DD
/V
of about
CAP
/V
PIC24FJ64GA004 FAMILY
CAP
Preliminary
pin
FIGURE 23-1:
23.2.2
When the voltage regulator is enabled, it takes approxi-
mately 20 μs for it to generate output. During this time,
designated as T
T
operation after any power-down, including Sleep mode.
If the regulator is disabled, a separate Power-up Timer
(PWRT) is automatically enabled. The PWRT adds a
fixed delay of 64 ms nominal delay at device start-up.
STARTUP
Note 1:
Regulator Disabled (DISVREG tied to V
Regulator Disabled (V
Regulator Enabled (DISVREG tied to V
(10 μF typ)
2.5V
2.5V
C
is applied every time the device resumes
EFC
ON-CHIP REGULATOR AND POR
(1)
(1)
These are typical operating voltages. Refer
to Section 26.1 “DC Characteristics” for
the full operating ranges of V
V
DDCORE
STARTUP
3.3V
3.3V
.
(1)
CONNECTIONS FOR THE
ON-CHIP REGULATOR
, code execution is disabled.
V
DISVREG
V
V
DD
V
DISVREG
V
V
DD
DDCORE
SS
V
DISVREG
V
V
PIC24FJ64GA
DD
DDCORE
SS
DD
DDCORE
SS
PIC24FJ64GA
PIC24FJ64GA
tied to V
/V
/V
/V
DS39881B-page 207
CAP
CAP
DDCORE
CAP
DD
and
SS
DD
):
):
):
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