PIC24FJ32GA002-I/SP Microchip Technology Inc., PIC24FJ32GA002-I/SP Datasheet - Page 193
![no-image](/images/manufacturer_photos/0/4/440/microchip_technology_inc__sml.jpg)
PIC24FJ32GA002-I/SP
Manufacturer Part Number
PIC24FJ32GA002-I/SP
Description
MCU, 16-Bit, 28-Pin, 32KB Flash, 8KB RAM, 21 I/O, Nanowatt
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC24FJ32GA002-ISP.pdf
(256 pages)
Specifications of PIC24FJ32GA002-I/SP
A/d Inputs
10 Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Memory Capacity
32 Kbytes
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
21
Number Of Pins
28
Package Type
28-pin SPDIP
Programmable Memory
32K Bytes
Ram Size
8K Bytes
Speed
32 MHz
Timers
5-16-bit
Voltage, Range
2-3.6 V
Voltage, Rating
2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC24FJ32GA002-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- Current page: 193 of 256
- Download datasheet (4Mb)
REGISTER 20-5:
REGISTER 20-6:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-0
Note 1:
PCFG7
CSSL7
R/W-0
R/W-0
U-0
U-0
—
—
Devices with 28 pins can use only PCFG0-PCFG5 and PCFG9-PCFG12.
Devices with 28 pins can use only CSSL0-CSSL5 and CSSL9-CSSL12.
Unimplemented: Read as ‘0’
PCFG12:PCFG0: Analog Input Pin Configuration Control bits
1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled
0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage
Unimplemented: Read as ‘0’
CSSL12:CSSL0: A/D Input Pin Scan Selection bits
1 = Corresponding analog channel selected for input scan
0 = Analog channel omitted from input scan
PCFG6
CSSL6
R/W-0
R/W-0
U-0
U-0
—
—
AD1PCFG: A/D PORT CONFIGURATION REGISTER
AD1CSSL: A/D INPUT SCAN SELECT REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
PCFG5
CSSL5
R/W-0
R/W-0
U-0
U-0
—
—
PCFG12
CSSL12
PCFG4
CSSL4
R/W-0
R/W-0
R/W-0
R/W-0
PIC24FJ64GA004 FAMILY
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PCFG11
CSSL11
PCFG3
CSSL3
R/W-0
R/W-0
R/W-0
R/W-0
(1)
PCFG10
CSSL10
PCFG2
CSSL2
R/W-0
R/W-0
R/W-0
R/W-0
(1)
x = Bit is unknown
x = Bit is unknown
PCFG9
PCFG1
CSSL9
CSSL1
R/W-0
R/W-0
R/W-0
R/W-0
DS39881B-page 191
PCFG8
PCFG0
CSSL8
CSSL0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0
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