USB3311C-CP-TR SMSC, USB3311C-CP-TR Datasheet - Page 3

• Manufacturer Part Number: USB3311C-CP-TR
• Description: TXRX USB ULPI 26MHZ CLK 24QFN
• Manufacturer: SMSC
• Series: flexPWR™r
• Type: USB Transceiverr

Specifications of USB3311C-CP-TR

• Protocol: USB 2.0
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-QFN
• Operating Supply Voltage: 3.3 V
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: 638-1096 - EVALUATION BOARD FOR USB3311C
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1091-2; USB3311C-CP

Hi-Speed USB Transceiver with 1.8V ULPI Interface - 26MHz Reference Clock
General Description
SMSC USB3311 REV C
VBUS
DM
DP
ID
The USB3311 is a highly integrated Hi-Speed USB 2.0 Transceiver (PHY) that supports systems
architectures based on a 26MHz reference clock. It is designed to be used in both commercial and
industrial temperature applications.
The USB3311 meets all of the electrical requirements to be used as a Hi-Speed USB Host, Device, or
an On-the-Go (OTG) device. In addition to the supporting USB signaling the USB3311 also provides
USB UART mode and USB Audio mode.
USB3311 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB PHY to the
Link. The industry standard ULPI interface uses a method of in-band signaling and status byte transfers
between the Link and PHY, to facilitate a USB session. By using in-band signaling and status byte
transfers the ULPI interface requires only 12 pins.
The USB3311 uses SMSC’s “wrapper-less” technology to implement the ULPI interface. This “wrapper-
less” technology allows the PHY to achieve a low latency transmit and receive time. SMSC’s low
latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By
adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused.
Transceiver
Hi-Speed
Carkit
OTG
USB
Figure 1 USB3311 Block Diagram
PRODUCT PREVIEW
Integrated
Low Jitter
Registers
and State
REFCLK
3
Machine
ULPI
PLL
Management
Integrated
Interface
DATA[7:0]
Power
BIAS
ULPI
Revision 2.1 (06-10-10)
RBIAS
RESETB
VBAT
VDD33
VDD18
STP
NXT
DIR
CLKOUT