PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 99
PIC18F452-I/L
Manufacturer Part Number
PIC18F452-I/L
Description
44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F452-IL.pdf
(332 pages)
Specifications of PIC18F452-I/L
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PLCC
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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9.5
This section is only applicable to the PIC18F4X2
devices.
PORTE is a 3-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register reads and writes the latched output value for
PORTE.
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7) which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
Register 9-1 shows the TRISE register, which also
controls the parallel slave port operation.
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as '0's.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
EXAMPLE 9-5:
© 2006 Microchip Technology Inc.
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVWF
Note:
PORTE, TRISE and LATE
Registers
PORTE
LATE
0x07
ADCON1
0x05
TRISE
On a Power-on Reset, these pins are
configured as analog inputs.
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; for digital inputs
; Value used to
; initialize data
; direction
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
INITIALIZING PORTE
FIGURE 9-9:
WR LATE
or
PORTE
WR TRISE
Note 1:
RD PORTE
Data
Bus
To Analog Converter
I/O pins have diode protection to V
TRIS Latch
Data Latch
D
D
CK
CK
RD LATE
RD TRISE
Q
Q
PORTE BLOCK DIAGRAM
IN I/O PORT MODE
PIC18FXX2
Q
EN
EN
D
Schmitt
Trigger
Input
Buffer
DS39564C-page 97
DD
and V
I/O pin
SS
.
(1)
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