PIC18F452-I/L Microchip Technology Inc., PIC18F452-I/L Datasheet - Page 94

• Manufacturer Part Number: PIC18F452-I/L
• Description: 44 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F452-I/L

• A/d Inputs: 8-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 10 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 36
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 44-pin PLCC
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 40 MHz
• Timers: 1-8-bit, 3-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC18FXX2
TABLE 9-3:
TABLE 9-4:
DS39564C-page 92
PORTB
LATB
TRISB
INTCON
INTCON2
INTCON3
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5/PGM
RB6/PGC
RB7/PGD
Legend: TTL = TTL input, ST = Schmitt Trigger input
Name
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Name
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
5: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB5 I/O function. LVP
(5)
(3)
LATB Data Output Register
PORTB Data Direction Register
must be disabled to enable RB5 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
INT2IP
RBPU
GIEH
Bit 7
GIE/
RB7
PORTB FUNCTIONS
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
INTEDG0
INT1IP
PEIE/
Bit 6
GIEL
Bit#
RB6
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
INTEDG1
TMR0IE
Buffer
Bit 5
RB5
TTL
—
(1)
(1)
(1)
(4)
(2)
(2)
(2)
INTEDG2
INT0IE
INT2IE
Input/output pin or external interrupt input0.
Internal software programmable weak pull-up.
Input/output pin or external interrupt input1.
Internal software programmable weak pull-up.
Input/output pin or external interrupt input2.
Internal software programmable weak pull-up.
Input/output pin or Capture2 input/Compare2 output/PWM output when
CCP2MX configuration bit is enabled.
Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low voltage ICSP enable pin.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming clock.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming data.
Bit 4
RB4
INT1IE
RBIE
Bit 3
RB3
—
TMR0IF
TMR0IP
Bit 2
RB2
—
INT0IF
INT2IF
Bit 1
RB1
—
Function
INT1IF
RBIP
Bit 0
RBIF
RB0
© 2006 Microchip Technology Inc.
xxxx xxxx
xxxx xxxx
1111 1111
0000 000x
1111 -1-1
11-0 0-00
POR, BOR
Value on
uuuu uuuu
uuuu uuuu
1111 1111
0000 000u
1111 -1-1
11-0 0-00
All Other
Value on
RESETS