PIC16F628A-I/P Microchip Technology Inc., PIC16F628A-I/P Datasheet - Page 71

• Manufacturer Part Number: PIC16F628A-I/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628A-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.1
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit baud rate generator. The SPBRG register controls
the period of a free running 8-bit timer. In Asynchro-
nous mode bit BRGH (TXSTA<2>) also controls the
baud rate. In Synchronous mode bit BRGH is ignored.
Table 12-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Given the desired baud rate and Fosc, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table 12-1. From this, the error in
baud rate can be determined.
Example 12-1 shows the calculation of the baud rate
error for the following conditions:
TABLE 12-1:
TABLE 12-2:
 2003 Microchip Technology Inc.
0
1
Legend:
98h
18h
99h
Legend:
Address
SYNC
F
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
OSC
USART Baud Rate Generator
(BRG)
= 16 MHz
X = value in SPBRG (0 to 255)
x = unknown, - = unimplemented read as '0'.
Shaded cells are not used by the BRG.
TXSTA
RCSTA
SPBRG
Name
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Baud Rate Generator Register
CSRC
SPEN
Bit 7
BRGH = 0 (Low Speed)
Bit 6
RX9
TX9
SREN
TXEN
Bit 5
OSC
OSC
/(4(X+1))
CREN
SYNC
Bit 4
/(64(X+1))
Preliminary
ADEN
Bit 3
—
EXAMPLE 12-1:
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register, causes the
BRG timer to be RESET (or cleared), this ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
BRGH
FERR
Bit 2
Desired Baud rate = F
Calculated Baud Rate = 16000000 / (64(25 + 1))
Error = (Calculated Baud Rate = Desired Baud Rate)
Baud Rate= F
NA
9600 = 16000000 / (64( +1 ))X
X = î25.042°
= 9615
= (9615 - 9600)/ 9600
= 0.16%
OERR
TRMT
Bit 1
OSC
/(16(X + 1)) equation can reduce the
BRGH = 1 (High Speed)
RX9D
Bit 0
TX9D
Desired Baud Rate
CALCULATING BAUD
RATE ERROR
OSC
OSC
PIC16F62X
/ (64(X + 1))
0000 -010
0000 -00x
0000 0000
/(16(X+1))
Value on
POR
DS40300C-page 69
Value on all
0000 -010
0000 -00x
0000 0000
RESETS
other