PIC16F628A-I/P Microchip Technology Inc., PIC16F628A-I/P Datasheet - Page 63

• Manufacturer Part Number: PIC16F628A-I/P
• Description: 18 PIN, 3.5 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F628A-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.0
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 11-1 shows the
timer resources of the CCP Module modes.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
REGISTER 11-1:
 2003 Microchip Technology Inc.
CAPTURE/COMPARE/PWM
(CCP) MODULE
bit 7-6
bit 5-4
bit 3-0
CCP1CON REGISTER (ADDRESS: 17h)
bit 7
Unimplemented: Read as '0'
CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRxL.
CCP1M3:CCP1M0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx = PWM mode
Legend:
R = Readable bit
-n = Value at POR
U-0
—
unaffected)
U-0
—
CCP1X
R/W-0
Preliminary
W = Writable bit
’1’ = Bit is set
CCP1Y
R/W-0
TABLE 11-1:
CCP Mode
CCP1M3
Compare
Capture
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
PWM
CCP MODE - TIMER
RESOURCE
CCP1M2 CCP1M1 CCP1M0
R/W-0
PIC16F62X
x = Bit is unknown
Timer Resource
R/W-0
DS40300C-page 61
Timer1
Timer1
Timer2
R/W-0
bit 0