PIC18F452-I/P Microchip Technology Inc., PIC18F452-I/P Datasheet - Page 289
PIC18F452-I/P
Manufacturer Part Number
PIC18F452-I/P
Description
40 PIN, 32 KB FLASH, 1536 RAM, 34 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F452-IP.pdf
(390 pages)
Specifications of PIC18F452-I/P
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
256 Bytes
Input Output
36
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
32K Bytes
Ram Size
1.5K Bytes
Speed
40 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
CNT
If CNT
If CNT
Q1
No
Q1
No
No
Q1
PC =
PC =
=
=
=
register ‘f’
operation
operation
operation
Decrement f, skip if 0
DECFSZ f {,d {,a}}
0
d
a
(f) – 1
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
Q2
Q2
No
No
No
Q2
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
f
[0,1]
[0,1]
255
by a 2-word instruction.
dest,
11da
GOTO
DECFSZ
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
95 (5Fh). See
ffff
CNT, 1, 1
LOOP
destination
operation
operation
operation
PIC18F2420/2520/4420/4520
Write to
Q4
Q4
Q4
No
No
No
ffff
Preliminary
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
TEMP
TEMP
If TEMP
If TEMP
Q1
Q1
No
Q1
No
No
PC
PC
register ‘f’
operation
operation
operation
Decrement f, skip if not 0
DCFSNZ
0
d
a
(f) – 1
skip if result
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
Q2
Q2
Q2
No
No
No
f
[0,1]
[0,1]
255
=
=
=
=
=
3 cycles if skip and followed
by a 2-word instruction.
dest,
DCFSNZ
:
:
f {,d {,a}}
11da
operation
operation
operation
?
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
0
Process
Data
Q3
Q3
No
Q3
No
No
DS39631A-page 287
95 (5Fh). See
ffff
TEMP, 1, 0
destination
operation
operation
operation
Write to
Q4
Q4
No
Q4
No
No
ffff
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