KSZ8721SL Micrel Inc, KSZ8721SL Datasheet - Page 12

• Manufacturer Part Number: KSZ8721SL
• Description: IC TXRX PHY 10/100 3.3V 48-SSOP
• Manufacturer: Micrel Inc
• Type: Transceiverr

Specifications of KSZ8721SL

• Number Of Drivers/receivers: 1/1
• Protocol: IEEE 802
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1630 - BOARD EVALUATION FOR KSZ8721SL
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1031-5; 576-1512-5; 576-1512-5; KSZ8721SL

Micrel, Inc.
SQE and Jabber Function (10BASE-T only)
In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a
test of the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL
goes high if TXEN is high for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BASE-T
transmitter is re-enabled and COL goes low.
Auto-Negotiation
The KS8721BL/SL performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It
automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its
link partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in
either full- or half-duplex mode (please refer to “Auto-Negotiation”). Auto-negotiation is disabled in the FX mode.
During auto-negotiation, the contents of Register 4, coded in fast link pulse (FLP), are sent to its link partner under the
conditions of power-on, link-loss, or restart. At the same time, the KS8721BL/SL monitors incoming data to determine
its mode of operation. The parallel detection circuit is enabled as soon as either 10BASE-T normal link pulse (NLP) or
100BASE-TX idle is detected. The operation mode is configured based on the following priority:
When the KS8721BL/SL receives a burst of FLP from its link partner with three identical link code words (ignoring
acknowledge bit), it will store these code words in Register 5 and wait for the next three identical code words. Once the
KS8721BL/SL detects the second code words, it then configures itself according to the above-mentioned priority. In
addition, the KS8721BL/SL also checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the
KS8721BL/SL automatically configures to match the detected operating speed.
MII Management Interface
The KS8721BL/SL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the
KS8721BL/SL. The MDIO interface consists of the following:
The INTPRT pin functions as a management data interrupt in the MII. An active Low or High in this pin indicates a
status change on the KS8721BL/SL based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits.
Register bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.
MII Data Interface
The data interface consists of separate channels for transmitting data from a 10/100 802.3 compliant Media Access
Controller (MAC) to the KS8721BL/SL, and for receiving data from the line. Normal data transmission is implemented in
4B nibble mode (4-bit wide nibbles).
Transmit Clock (TXC)
The transmit clock is normally generated by the KS8721BL/SL from an external 25MHz reference source at the X1
input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KS8721BL/SL
normally samples these signals on the rising edge of the TXC.
Receive Clock (RXC)
For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down, and auto-
negotiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BASE-T links, the
June 2009
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Priority 1: 100BASE-TX, full-duplex
Priority 2: 100BASE-TX, half-duplex
Priority 3: 10BASE-T, full-duplex
Priority 4: 10BASE-T, half-duplex
A physical connection including a data line (MDIO), a clock line (MDC), and an optional interrupt line (INTRPT).
A specific protocol that runs across the above-mentioned physical connection that allows one controller to
communicate with multiple KS8721BL/SL devices. Each KS8721BL/SL is assigned an MII address between 0
and 31 by the PHYAD inputs.
An internal addressable set of fourteen 16-bit MDIO registers. Registers [0:6] are required and their functions
are specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.
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M9999-062509-1.3
KS8721BL/SL