KSZ8721SL Micrel Inc, KSZ8721SL Datasheet - Page 10
![IC TXRX PHY 10/100 3.3V 48-SSOP](/photos/6/84/68448/576-48-ssop_sml.jpg)
KSZ8721SL
Manufacturer Part Number
KSZ8721SL
Description
IC TXRX PHY 10/100 3.3V 48-SSOP
Manufacturer
Micrel Inc
Type
Transceiverr
Datasheet
1.KSZ8721SL.pdf
(35 pages)
Specifications of KSZ8721SL
Number Of Drivers/receivers
1/1
Protocol
IEEE 802
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
576-1630 - BOARD EVALUATION FOR KSZ8721SL
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
576-1031-5
576-1512-5
576-1512-5
KSZ8721SL
576-1512-5
576-1512-5
KSZ8721SL
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
KSZ8721SL
Manufacturer:
MICREL
Quantity:
21
Company:
Part Number:
KSZ8721SL
Manufacturer:
KENDIN
Quantity:
3
Part Number:
KSZ8721SL
Manufacturer:
MICREL/麦瑞
Quantity:
20 000
Company:
Part Number:
KSZ8721SL TR
Manufacturer:
Micrel
Quantity:
6 656
Micrel, Inc.
Strapping Options
Notes:
June 2009
Pin Number
1.
2.
3.
6, 5,
11
21
22
4, 3
9
25
27
28
29
30
(3)
(3)
(3)
(3)
Strap-in is latched during power-up or reset.
Ipu = Input with internal pull-up.
Ipd/O = Input with internal pull-down during reset; output pin otherwise.
Ipu/O = Input with internal pull-up during reset; output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
Some devices may drive MII pins that are designated as output (PHY) on power-up, resulting in incorrect strapping values latched at reset.
It is recommended that an external pull-down via 1kΩ resistor be used in these applications to augment the 8721’s internal pull-down.
PHYAD[4:1]/
PCS_LPBK/
ISO/RXER
RMII_BTB
NWAYEN/
Pin Name
RMII/COL
PHYAD0/
DUPLEX/
RXD[0:3]
SPD100/
No FEF/
RXDV
LED2
LED3
INT#
CRS
PD#
(1)
Type
Ipd/O
Ipu/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipu/O
Ipu/O
Ipu/O
Ipu
(2)
Pin Function
PHY Address latched at power-up/reset. The default PHY address is 00001.
Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables ISOLATE mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enables RMII mode at power-up/reset. PD (default) = Disable, PU = Enable.
Enable RMII back-to-back mode at power-up/reset. PD (default) = Disable,
PU = Enable.
Latched into Register 0h bit 13 during power-up/reset. PD = 10Mbps, PU (default) =
100Mbps. If SPD100 is asserted during power-up/reset, this pin is also latched as
LED1 the Speed Support in register 4h. (If FXEN is pulled up, the latched value 0
means no Far_End _Fault.)
Latched into Register 0h bit 8 during power-up/reset. PD = Half-duplex, PU (default) =
Full-duplex. If Duplex is pulled up during reset, this pin is also latched as the Duplex
support in register 4h.
Nway (auto-negotiation) Enable. Latched into Register 0h bit 12 during power-up/reset.
PD = Disable Auto-Negotiation, PU (default) = Enable Auto-Negotiation.
Power-Down Enable. PU (default) = Normal operation, PD = Power-Down mode.
10
M9999-062509-1.3
KS8721BL/SL