BU2092F-E2 Rohm Semiconductor, BU2092F-E2 Datasheet - Page 12

• Manufacturer Part Number: BU2092F-E2
• Description: IC DRIVER 12BIT S-IN P-OUT SOP18
• Manufacturer: Rohm Semiconductor
• Type: Driverr

Specifications of BU2092F-E2

• Number Of Drivers/receivers: 12/0
• Voltage - Supply: 2.7 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 18-SOP
• Output Current: 25mA
• No. Of Outputs: 12
• Supply Voltage Range: 2.7V To 5.5V
• Driver Case Style: SOP
• No. Of Pins: 18
• Operating Temperature Range: -20°C To +75°C
• Svhc: No SVHC (18-Jun-2010)
• Base: RoHS Compliant
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current: 0.025 A
• Maximum Operating Temperature: + 75 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 25 C
• Output Voltage: 2 V to 1 V
• Base Number: 2092
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Protocol: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: BU2092F-E2TR

【BU2099FV】
●Pin descriptions
●Timing chart
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＊The Q0～Q11 output have a Nch open drain Tr. The Tr is ON when data from shift register is “L”, and Tr is OFF when data is “H”.
Input
Pin No.
CLOCK
6 ～ 17
SO
CLOCK
DATA
LCK
OE
18
19
20
Qx
1
2
3
4
5
×
×
×
×
1.
2.
3.
4.
5.
［ Truth Table ］
After the power is turned on and the voltage is stabilized, LCK should be activates, after clocking 12 data bits into
the DATA terminal.
Qx parallel output data of the shift register is set after the 12
Since the LCK is a label latch, data is retained in the “L” section and renewed in the “H” section of the LCK.
Data retained in the internal latch circuit is output when the OE is in the “L” section.
The final stage data of the shift register is output to the SO by synchronizing with the rise time of the CLOCK.
Pin Name
Q0 ～ Q11
CLOCK
DATA
DATA
N.C.
LCK
(Qx)
V
V
SO
OE
H
×
×
L
×
×
×
SS
DD
Previous
DATA 11
DATA12
“H”
LCK
×
×
×
×
×
Previous
DATA 11
DATA11
I/O
O
O
-
-
-
I
I
I
I
Previous DATA
OE
Function
GND
Non connected
Serial Data Input
Shift clock of Shift register (Rising Edge Trigger)
Latch clock of Storage register (Rising Edge Trigger)
Parallel Data Output (Nch Open Drain FET)
Serial Data Output
Output Enable Control Input
Power Supply
H
L
×
×
×
×
×
DATA10
Latch Data
Output FET
Function
All the output data output “H” with pull-up.
The Q0 ～ Q11 output can be enable and output the data of storage register.
Store “L” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
Store “H” in the first stage data of shift register, the previous stage data in the
others. (The conditions of storage register and output have no change.)
The data of shift register has no change.
SO outputs the final stage data of shift register with synchronized falling
edge of CLOCK, not controlled by OE.
The data of shift register is transferred to the storage register.
The data of storage register has no change.
12/24
Fig. 7
ON
L
＊OE pin is pulled down to Vss.
th
clock by the LCK.
DATA2
OFF
H
DATA1
DATA12
Technical Note
2009.06 - Rev.A
DATA11
DATA