GAL16V8D-25LPN Lattice, GAL16V8D-25LPN Datasheet

GAL16V8D-25LPN

Manufacturer Part Number

GAL16V8D-25LPN

Description

PLD; Programmable AND-Array Logic; 20-Pin PDIP; -0.5 to V; 75 mA; 0.8 V, 25 nS

Manufacturer

Lattice

Datasheet

1.GAL16V8D-25LPN.pdf (7 pages)

Specifications of GAL16V8D-25LPN

Circuit Type

Advanced

Current, Supply

75 mA

Logic Function

Programmable

Logic Type

CMOS

Package Type

PDIP-20

Special Features

High Speed

Temperature, Operating, Range

0 to +75 °C

Voltage, Supply

4.75 to 5.25 V

Lead Free Status / Rohs Status

RoHS Compliant part Electrostatic Device

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• HIGH PERFORMANCE E

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

• ACTIVE PULL-UPS ON ALL PINS

• E

• EIGHT OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

The GAL16V8, at 3.5 ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

able (E

performance available in the PLD market. High speed erase times

(<100ms) allow the devices to be reprogrammed quickly and ef-

ficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configura-

tions possible with the GAL16V8 are the PAL architectures listed

in the table of the macrocell description section. GAL16V8 devices

are capable of emulating any of these PAL architectures with full

function/fuse map/parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP

16v8_11

Features

Description

— 3.5 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 3.0 ns Maximum from Clock Input to Data Output

— UltraMOS

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Also Emulates 20-pin PAL

— 100% Functional Testability

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

CELL TECHNOLOGY

Function/Fuse Map/Parametric Compatibility

) floating gate technology to provide the highest speed

Advanced CMOS Technology

CMOS

Devices with Full

TECHNOLOGY

I/CLK

Functional Block Diagram

Pin Configuration

I/CLK

GND

GAL16V8

GND

Top View

PLCC

SOIC

16V8

GAL

View

Top

I/CLK

I/OE

High Performance E

Vcc

I/O/Q

Vcc

I/O/Q

I/OE

I/O/Q

Generic Array Logic™

GAL16V8

I/CLK

GND

CLK

OLMC

16V8

CMOS PLD

GAL

DIP

I/O/Q

I/OE

Vcc

I/O/Q

I/OE

Related parts for GAL16V8D-25LPN

GAL16V8D-25LPN Summary of contents

Page 1

... GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...

Page 2

... Lead-Free Packaging Commercial Grade Specifications Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory. Industrial Grade Specifications Part Number Description GAL16V8D Device Name Speed (ns Low Power Power Q = Quarter Power XXXXXXXX Specifications GAL16V8 Grade Blank = Commercial I = Industrial Package P = Plastic DIP PN = Lead-free Plastic DIP ...

Page 3

Output Logic Macrocell (OLMC) The following discussion pertains to configuring the output logic macrocell. It should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. There are three global OLMC ...

Page 4

... The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T A Specifications GAL16V8D Recommended Operating Conditions (1) Commercial Devices: +1.0V ...

Page 5

... Refer to fmax Descriptions section. Characterized but not 100% tested. 4) Characterized but not 100% tested. Capacitance ( ° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL16V8D Over Recommended Operating Conditions MAXIMUM* UNITS COM COM COM / IND - UNITS MIN ...

Page 6

... Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance ( ° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL16V8D Specifications GAL16V8 Over Recommended Operating Conditions COM / IND -10 MIN. MAX — 6 7.5 — ...

Page 7

... Input Rise and Fall Times GAL16V8D-3/-5/-7 Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GAL16V8D (except -3) Output Load Conditions (see figure above) Test Condition 200Ω B Active High ∞ ...

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