AD9850BRSZ Analog Devices Inc, AD9850BRSZ Datasheet - Page 11

• Manufacturer Part Number: AD9850BRSZ
• Description: IC DDS SYNTHESIZER CMOS 28-SSOP
• Manufacturer: Analog Devices Inc

Specifications of AD9850BRSZ

• Mounting Type: Surface Mount
• Resolution (bits): 10 b
• Master Fclk: 125MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Rf Ic Case Style: SSOP
• No. Of Pins: 28
• Supply Voltage Range: 4.75V To 5.25V, 3.3V
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 3 - 168 Hours
• Frequency Max: 125MHz
• Current Rating: 30A
• Frequency: 125MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. H
COS OUT
DAC STROBE
RESET
Figure 8. Parallel Load Power-Down Sequence/Internal Operation
CLKIN
DATA (W0)
DATA (W0)
Figure 9. Parallel Load Power-Up Sequence/Internal Operation
W CLK
W CLK
FQ UD
FQ UD
CLKIN
CLKIN
NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME
NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT
HAVE TO BE SYNCHRONOUS WITH THE CLKIN IF THE MINIMAL TIME IS NOT REQUIRED.
RESULTS OF RESET:
SYMBOL
t
t
t
t
t
RH
RL
RR
RS
OL
Figure 7. Master Reset Timing Sequence
– FREQUENCY/PHASE REGISTER SET TO 0
– ADDRESS POINTER RESET TO W0
– POWER-DOWN BIT RESET TO 0
– DATA INPUT REGISTER UNEFFECTED
t
RH
DEFINITION
CLK DELAY AFTER RESET RISING EDGE
RESET FALLING EDGE AFTER CLK
RECOVERY FROM RESET
MINIMUM RESET WIDTH
RESET OUTPUT LATENCY
INTERNAL CLOCKS ENABLED
t
RS
XXXXX000
XXXXX100
–11–
t
OL
t
RL
INTERNAL CLOCKS DISABLED
t
RR
MINIMUM
3.5ns
3.5ns
2 CLK CYCLES
5 CLK CYCLES
13 CLK CYCLES
COS (0)
AD9850