SAB 82525 N V2.2 Infineon Technologies, SAB 82525 N V2.2 Datasheet - Page 105

• Manufacturer Part Number: SAB 82525 N V2.2
• Description: IC CONTROLLER HSCX PLCC-44
• Manufacturer: Infineon Technologies

Specifications of SAB 82525 N V2.2

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAB82525NV2.2XT; SAB82525NV22XK; SP000063649; SP000084997

ITF/OIN … Interframe Time Fill/One Insertion
ODS … Output Driver Select
CM2, CM1, CMO … Clock Mode
Note:
Semiconductor Group
The function of this bit depends on the selected serial port configuration (bit SC0)
Defines the function of the transmit data pins (T DA, T DB)
0. . .T D pins are open drain outputs
1. . .T D pins are push-pull outputs
Selects one of the 8 different clock modes
000
.
.
.
111
Point-to-point configurations: ITF
Determines the idle (= no data to send) state of the transmit data pins (T DA, T DB)
0 … Continuous IDLE sequences are output (T D pins remain in the "1" state)
1 … Continuous FLAG sequences are output ("01111110" bit patterns)
Bus configurations: OIN
In bus configurations, the ITF is implicitly set to 0, i.e. continuous "1"s are transmitted,
and data encoding is NRZ!
When this bit is set, a "ONE" insertion (deletion) mechanism is activated, inserting a "1"
after seven consecutive "0"s in the transmit data stream or deleting a "1" in the receive
data stream.
Similar to the HDLC’s bit-stuffing mechanism (inserting a "0" after five consecutive "1"s),
this method proves to be advantageous when the receive clock is recovered from the
receive data stream by means of DPLL, because it is guaranteed that at least after seven
bits a transition occurs in the receive data in case of long "0" sequences!
Since in time-slot oriented systems the T D pin is not tristated automatically out of the
programmed time-slot, the T
oriented bus systems.
clock mode 0
.
.
.
clock mode 7
D pin should be configured as open drain in time-slot
105
SAB 82525
SAB 82526
SAF 82525
SAF 82526