RC82562EP Intel, RC82562EP Datasheet - Page 77
RC82562EP
Manufacturer Part Number
RC82562EP
Description
IC ETH 10/100 PLC DEV CTRL 64BGA
Manufacturer
Intel
Specifications of RC82562EP
Rohs Status
RoHS non-compliant
Controller Type
Ethernet Controller
Interface
IEEE 802.3
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
64-BGA
Current - Supply
-
Operating Temperature
-
Other names
832361
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Intel 8255x 10/100 Mbps Ethernet Controller Family Open Source Software Developer Manual
Note:
— Bit 4 - Extended Transmit CB (TxCB). This bit is reserved on the 82557 and should be set
— Bit 3 - CI Interrupt = CU Idle Interrupt. This bit determines whether the device generates
— Bit 2. This bit is only used on the 82557 and 82559. However, it has a completely different
it is set to 1, the device dumps the 82557 compatible 16 counters into 68 bytes of memory.
If the bit is 0, the device dumps the full 19 counters into 80 bytes of memory.
0 = Extended Statistical Counters.
1 = Standard Statistical Counters.
Default - 1 (standard statistical counters).
Recommended - 1.
to 1. However, for the 82558 or 82559, it determines the type of TxCB that is to be used
by the device.
If this bit is 1, the device reads the standard 4 Dword TxCB. When this bit equals 0, the
device reads 8 Dwords for all CBs and processes the TxCBs as Extended TxCBs as
described in
0 = Extended TxCB.
1 = Standard TxCB.
Default - 1 (Standard TxCB).
Recommended - 1 for compatibility reasons. If performance is the main criteria, it is
recommended that this bit equal 0.
an interrupt when the CU leaves the Active state (CNA interrupt) or when the CU enters
the Idle state (CI interrupt). If CNA interrupt is enabled, the device will generate an
interrupt when the CU goes from the Active to a non-active state (Idle or Suspended).
Interrupts are generated whenever the device sees an EL or S bit in a CB that causes it to
go into the Idle or Suspended state respectively on completion of the command. The CI
interrupt will generate interrupts only on a transition from an Active to the Idle state. If the
CI mode is enabled, interrupts can be generated in dynamic chaining (suspend/resume) by
setting the I-bit on individual CBs.
0 = CNA Interrupt. An interrupt is generated when the CU goes from active to idle or
suspended state.
1 = CI Interrupt. An interrupt is generated when the CU goes from the active to the idle
state.
Default - 0 (CNA interrupt).
Recommended - 0, depending on the implementation of the transmit code.
meaning for both devices. For the 82557, it is the TNO Interrupt = Transmit Not OK
Interrupt (82557 only), and for the 82559, the TCO Statistical Counter.
For the 82557, this bit determines whether or not the device generates an interrupt when a
transmission ends with a bad status. If it is configured to TNO Interrupt, the device
generates an interrupt by setting the CX interrupt bit in the SCB register and asserting the
INTA# signal. This interrupt is related to the completion of actual transmission on the link
and cannot be correlated to a specific transmit CB status. The status of the bad
transmission is reflected only in a statistical manner through the statistical counters.
0 = CX Interrupt only.
1 = TNO Interrupt enabled.
For the 82559, setting this bit to 1 causes the device to provide TCO statistical counters.
In this case, the statistical counters are 24-Dword long structures with the last 4 Dwords.
When it is configured to TNO Interrupt, the 82557 still generates a CX interrupt if
it encounters a transmit CB with its I bit set.
Section 6.4.2.5, “Transmit
(100b)”.
Host Software Interface
69
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