DP83907VF National Semiconductor, DP83907VF Datasheet - Page 49

• Manufacturer Part Number: DP83907VF
• Description: IC CONTROLLR AT/LANII TP 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83907VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83907VF

6 0 Operation of DP83907
For the following alignment in the FIFO the packet length
should be (N x 8)
TCR is set CRC will not be appended by the transmitter If
the CRC is appended by the transmitter the 1st four bytes
bytes N-3 to N correspond to the CRC
Loopback Tests
Loopback capabilities are provided to allow certain tests to
be performed to validate operation of the DP83907 prior to
transmitting and receiving packets on a live network Typi-
cally these tests may be performed during power up of a
node The diagnostic provides support to verify the follow-
ing
1) Verify integrity of data path Received data is checked
2) Verify CRC logic’s capability to generate good CRC on
3) Verify that the Address Recognition Logic can
Loopback Operation In the DP83907 Controller
Loopback is a modified form of transmission using only half
of the FIFO This places certain restrictions on the use of
Ioopback testing When loopback mode is selected in the
TCR the FIFO is spilt A packet should be assembled in
memory with programming of TPSR and TBCR0 TBCR1
registers When the transmit command is issued the follow-
ing operations occur
TRANSMITTER ACTIONS
1) Data is transferred from memory by the DMA until the
2) The DP83907 generates 56 bits of preamble followed by
3) Data transferred from FIFO to serializer
4) If CRC
5) At end of Transmission PTX bit set in ISR
Location
against transmitted data
transmit verify CRC on receive (good or bad CRC)
a) Recognize address match packets
b) Reject packets that fail to match an address
FIFO is filled For each transfer TBCR0 and TBCR1 are
decremented (Subsequent burst transfers are initiated
when the number of bytes in the FIFO drops below the
programmed threshold )
an 8-bit synch pattern
last byte transmitted is the last byte from the FIFO (Al-
lows software CRC to be appended) If CRC
DP83907 calculates and appends four bytes of CRC
FIFO
0
1
2
3
4
5
6
7
e
1 in TCR no CRC calculated by DP83907 the
Lower Byte Count
Upper Byte Count
Upper Byte Count
Byte N-3 (CRC1)
Byte N-2 (CRC2)
Byte N-1 (CRC3)
FIFO Contents
Byte N (CRC4)
a
Byte N-4
5 Bytes Note that if the CRC bit in the
Second Byte Read
(Continued)
First Byte Read
Last Byte Read
e
0
49
RECEIVER ACTIONS
1) Wait for synch all preamble stripped
2) Store packet in FIFO increment receive byte count for
3) If CRC
4) At end of receive receive byte count written into FIFO
EXAMPLES
The following examples show what results can be expected
from a properly operating DP83907 during loopback The
restrictions and results of each type of loopback are listed
for reference The loopback tests are divided into two sets
of tests One to verify the data path CRC generation and
byte count through all three paths The second set of tests
uses internal loopback to verify the receiver’s CRC checking
and address recognition For all of the tests the DCR was
programmed to 40H
Note 1 Since carrier sense and collision detect are generated in the ENDEC
module They are blocked during internal loopbaok carrier and CD heartbeat
are not seen and the CRS and CDH bits are set
Note 2 CRC errors are always indicated by receiver if CRC is appended by
the transmitter
Note 3 Only the PTX bit in the ISR is set the PRX bit is only set if status is
written to memory In loopback this action does not occur and the PRX bit
remains 0 for all loopbaok modes
Note 4 All values are hex
Note 1 CDH is set CRS is not set since it is generated by the external
encoder decoder
Note 1 CDH and CRS should not be set The TSR however could also
contaln 01H 03H 07H and a variety of other values depending on whether
collisions were encountered or the packet was deferred
Note 2 Will contain O8H if packet is not transmittable
Note 3 During external loopback the DP83907 Controller is now exposed to
network traffic it is therefore possible for the contents of both the Receive
portion of the FIFO and the RSR to be corrupted by any other paoket on the
network Thus in a live network the contents of the FIF0 and RSR should not
be depended on The DP83907 will still abide by the standard CSMA CD
protocol in external loopback mode (i e The network will not be disturbed
by the loopback paoket)
Note 4 All values are hex
DP83907
DP83907
DP83907
Internal
Internal
Internal
each incoming byte
CRC errors If CRC
CRC errors CRC error bit always set in RSR (for address
matching packets)
receive status register is updated The PRX bit is typical-
ly set in the RSR even if the address does not match If
CRC errors are forced the packet must match the ad-
dress filters in order for the CRC error bit in the RS to be
set
Path
Path
Path
e
TCR
0 in TRC receiver checks incoming packet for
TCR
02
TCR
06
04
RCR
00
RCR
e
00
RCR
00
1 in TCR receiver does not check
(Note 1)
TSR
(Note 1)
53
TSR
(Note 1)
03
TSR
43
(Note 2)
RSR
RSR
02
02
RSR
02
(Note 2)
(Note 3)
ISR
ISR
02
02
ISR
02