DP83907VF National Semiconductor, DP83907VF Datasheet - Page 22

• Manufacturer Part Number: DP83907VF
• Description: IC CONTROLLR AT/LANII TP 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83907VF

• Controller Type: Network Interface Controller (NIC)
• Interface: Twisted Pair
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83907VF

4 0 Functional Description
Manchester Decoder
The decoder consists of a differential receiver and a PLL to
separate a Manchester encoded data stream into internal
clock signals and data The differential input must be exter-
nally terminated with two 39
if the standard 78
Ethernet applications these resistors are optional To pre-
vent noise from falsely triggering the decoder a squelch
circuit at the input rejects signals with levels less than
comes valid typically within 6-bit times The DP83907 may
tolerate bit jitter up to 20 ns in the received data The decod-
er detects the end of a frame when no more mid-bit tran-
sitions are detected
Collision Translator
When in AUI Mode the Ethernet transceiver (DP8392 CTI)
detects a collision it generates a 10 MHz signal to the dif-
ferential collision inputs (CD
these inputs are detected active the DP83907 uses this
signal to back off its current transmission and reschedule
another one
In this mode the COL led output will indicate when the
CD
means it will correctly indicate any collision on the network
but will not be lit for heartbeat or if there is no cable con-
nected
The collision differential inputs are terminated the same way
as the differential receive inputs The squelch circuitry is
also similar rejecting pulses levels less than
b
175 mV Signals more negative than
a
lines are active during activity on the network This
transceiver drop cable is used In thin
g
resistors connected in series
) of the DP83907 When
b
300 mV Data be-
(Continued)
b
175 mV
22
AV
The AV
loop (PLL) of the ENDEC unit Since this is an analog circuit
excessive noise on the AV
ance of the PLL This noise if in the 10 KHz– 400 KHz
range can reduce the jitter performance of the ENDEC re-
sulting in missing packets or CRC errors
If the power supply noise is causing significant packet re-
ception error a low pass filter could be added to reduce the
power supply noise and hence improve the jitter perform-
ance Standard analog design techniques should be utilized
when laying out the power supply traces on the board If the
digital power supply is used it may be desirable to add a
one pole RC filter (designed to have a cut-off frequency of
1 KHz) as shown in Figure 22 to improve the jitter perform-
ance The AV
the resister is less than 90 mV which will not affect the
PLL’s operation
CC
Power Supply Consideration
CC
FIGURE 22 Filtering Power Supply Noise
pin is the
CC
draws 3 mA– 4 mA so the voltage across
a
5V power supply for the phase lock
CC
pin can affect the perform-
TL F 12082 – 17