DP83850CVF National Semiconductor, DP83850CVF Datasheet - Page 8

• Manufacturer Part Number: DP83850CVF
• Description: IC CONTROLLER INTERFACE 132-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83850CVF

• Controller Type: Ethernet Repeater Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 295mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83850CVF

2.0 Pin Descriptions
2.3 EEPROM Interface
2.4 Miscellaneous
/IR_BUS_EN
RDIO
RDC
/SDV
/ACTIVEO
Note: A table showing pin type designation is given in section 2.5
LCK
RID[4:0]
/RST
GRDIO
BRDC
RDIR
Signal Name Type Active
Signal Name
Signal Name
EE_DO
EE_CS
EE_CK
EE_DI
O, L
O, L
O, L
O/OC, M
I
I/O/Z, L
I/O/Z, L
Type
Type
O, L
O, L
O,L
I
I
I
I
I
high
-
-
-
Active
Active
high
(Continued)
low
low
low
low
EEPROM Chip Select: Asserted during reads to EEPROM.
EEPROM Serial Clock: Local Clock
EEPROM Serial Data Out: Connected to the serial data out of the EEPROM.
EEPROM Serial Data In: Connected to the serial data in of the EEPROM.
—
—
—
—
—
—
Inter-Repeater Bus Enable: This signal is asserted at all times (either when the
100RIC is driving the bus or receiving from the bus) and it is deasserted only when
the 100RIC switches direction from an input (receiving) mode to an output (driving)
mode. After this switch, this signal becomes asserted again.
Register Data I/O: Serial data input/output transfers data to/from the internal regis-
ters. Serial protocol conforms to the IEEE 802.3u MII (Media Independent Interface)
specification.
Note: Input buffer has a weak pull-up.
Register Data Clock: All data transfers on RDIO are synchronized to the rising edge
of this clock. RDC is limited to a maximum frequency of 2.5 MHz. At least 3 cycles
of RDC must be provided during assertion of /RST (pin 103) to ensure proper reset
of all internal blocks.
Serial Data Valid: Asserted when a valid read or write command is present. Used to
detect disconnection of the management bus so that synchronization is not lost. If not
used, tie this pin to GND.
Note: Input buffer has a weak pull-up.
Active Out: Enable for the IR_VECT[4:0] and /IR_ACTIVE signals. Used in multi-
DP83850C systems to enable the external buffers driving these Inter Repeater Bus
signals.
A pull up of 680 1/2 must be used with this signal.
Local Clock: Must be 25 MHz
devices, TX Bus data transfers and DP83850C internal state machines.
Repeater Identification Number: Provides the unique vector for the IR_VECT[4:0]
signals used in Inter Repeater bus arbitration. These bit are also used to uniquely iden-
tify this chip for serial register accesses. The RID value is latched when reset is de-
asserted.
Note: The arbiter cannot use the value 1Fh as its arbitration vector. This is the
IR_VECT[4:0] bus idle state, therefore RID[4:0] must never be set to this value.
Reset: The chip is reset when this signal is asserted low.
Gated Register Data Input/Output: This I/O is a gated version of RDIO. When the
“phy_access” bit in the CONFIG register is set high, the RDIO signal is passed through
to GRDIO for accessing the physical layer chips.
Note: Input buffer has a weak pull-up.
Buffered Register Data Clock: Buffered version of RDC. Allows more devices to be
chained on the MII serial bus.
Register Data Direction: Direction signal for an external bi-directional buffer on the
RDIO signal.
Defaults to 0 when no register access is present.
0 = RDIO data flows into the DP83850C
1 = RDIO data flows out of the DP83850C
8
Pin Description
32 = 0.78125MHz
50ppm. Used for TX data transfer to Physical Layer
Pin Description
Description
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