DP83850CVF National Semiconductor, DP83850CVF Datasheet - Page 16

• Manufacturer Part Number: DP83850CVF
• Description: IC CONTROLLER INTERFACE 132-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83850CVF

• Controller Type: Ethernet Repeater Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 295mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83850CVF

4.0 Registers
The DP83850C has 64 registers in 2 pages of 32 16-bit registers. At power-on and/or reset, the DP83850C defaults to
Page 0 registers. The register page can be changed by writing to the PAGE register in either register page. The register
page maps are given in sections 4.1 and 4.2, followed by a detailed description of the registers in sections 4.3 to 4.12.
4.1 Page 0 Register Map
Address
1C - 1F P5_SE ...
18 - 1B P4_SE ...
10 - 13
14 - 17
(hex)
C
D
0
1
2
3
4
5
6
7
8
9
A
B
E
F
CONFIG
PAGE
PARTITION read only Indicates Auto-Partitioning status.
JABBER
ADMIN
DEVICEID
HUBID0
HUBID1
P0_SE
P0_LE
P0_COL
P0_PART
P1_SE
P1_LE
P1_COL
P1_PART
P2_SE ...
P2_PART
P3_SE ...
P3_PART
P4_PART
P5_PART
Name
read only Indicates Jabber status.
read only First 16 bits read from EEPROM.
read only Second 16 bits read from EEPROM.
Access
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Sets the DP83850C configuration.
Selects either register page 0 or 1.
Port enable/disable, administration control/status.
Accesses a) the DP83850C ID number configured externally on the RID[4:0] pins and
b) the last receiving port number. The DP83850C device number may be overwritten
after it has been latched at the end of reset: be careful not to have duplicate ID’s on
the same IR bus interface.
Port 0: 32-bit ShortEvent counter (See access rules section 4.11).
Port 0: 32-bit LateEvent counter (See access rules section 4.11).
Port 0: 32-bit Collision counter (See access rules section 4.11).
Port 0: 16-bit Auto-Partition counter.
Port 1: 32-bit ShortEvent counter (See access rules section 4.11).
Port 1: 32-bit LateEvent counter (See access rules section 4.11).
Port 1: 32-bit Collision counter (See access rules section 4.11).
Port 1: 16-bit Auto-Partition counter.
Port 2 management counters (as per ports 0, 1 above).
Port 3 management counters (as per ports 0, 1 above).
Port 4 management counters (as per ports 0, 1 above).
Port 5 management counters (as per ports 0, 1 above).
16
Description
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