DP8409AN-2 National Semiconductor, DP8409AN-2 Datasheet - Page 3

• Manufacturer Part Number: DP8409AN-2
• Description: IC CONTROLLER DYNAMIC RAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8409AN-2

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN-2

Pin Definitions
Mode
CASIN (RGCK) In Auto-Refresh Mode Auto Burst Mode
and All-RAS Auto-Write Mode this pin is the RAS Generator
Clock input In all other modes it is CASIN (Column Address
Strobe Input) which inhibits CAS output when high in
Modes 4 and 3b In Mode 6 it can be used to prolong CAS
output
ADS Address (Latch) Strobe Input Row Address Col-
umn Address and Bank Select Latches are fall-through with
ADS high Latches on high-to-low transition
CS Chip Select Input The TRI-STATE mode will Address
Outputs and puts the control signal into a high-impedance
logic ‘‘1’’ state when high (unless refreshing in one of the
Refresh Modes) Enables all outputs when low
M0 M1 M2 Mode Control Inputs These 3 control pins
determine the 8 major modes of operation of the DP8409A
as depicted in Table I
RF I O The I O pin functions as a Reset Counter Input
when set low from an external open-collector gate or as a
flag output The flag goes active-low in Modes 0 and 2 when
the End-of-Count output is at 127 255 or 511 (see
Table III) In Auto-Refresh Mode it is the Refresh Request
output
WIN Write Enable Input
WE Write Enable Output Buffered output from WIN
CAS Column Address Strobe Output In Modes 3a 5
and 6 CAS transitions low following valid column address
In Modes 3b and 4 it goes low after R C goes low or fol-
lows CASIN going low if R C is already low CAS is high
duing refresh
RAS 0 –3 Row Address Strobe Outputs Selects a mem-
ory bank decoded from B1 and B0 (see Table II) if RFSH is
high If RFSH is low all banks are selected
B0 B1 Bank Select Inputs Strobed by ADS Decoded to
enable one of the RAS outputs when RASIN goes low Also
used to define End-of-Count in Mode 7 (Table III)
Conditions for All Modes
INPUT ADDRESSING
The address block consists of a row-address latch a col-
umn-address latch and a resettable refresh counter The
address latches are fall-through when ADS is high and latch
when ADS goes low If the address bus contains valid ad-
dresses until after the valid address time ADS can be per-
3a
3b
0
1
2
4
5
6
7
(RFSH)
M2
0
0
0
0
0
1
1
1
1
(Continued)
M1
0
0
1
1
1
0
0
1
1
M0
0
1
0
1
1
0
1
0
1
TABLE I DP8409A Mode Select Options
Externally Controlled Refresh
Auto Refresh Forced
Internal Auto Burst Refresh
All RAS Auto Write
Externally Controlled All RAS Access
Externally Controlled Access
Auto Access Slow t
Auto Access Fast t
Set End of Count
Mode of Operation
3
RAH
RAH
manently high Otherwise ADS must go low while the ad-
dresses are still valid
In normal memory access operation RASIN and R C are
initially high When the address inputs are enabled into the
address latches the row addresses appear on the Q out-
puts The address strobe also inputs the bank-select ad-
dress (B0 and B1) If CS is low all outputs are enabled
When CS is transitioned high the address outputs go TRI-
STATE and the control outputs first go high through a low
impedance and then are held by an on-chip high imped-
ance This allows output paralleling with other DP8409As for
multi-addressing All outputs go active about 50 ns after the
chip is selected again If CS is high and a refresh cycle
begins all the outputs become active until the end of the
refresh cycle
DRIVE CAPABILITY
The DP8409A has timing parameters that are specified with
up to 600 pF loads In a typical memory system this is equiv-
alent to about 88 5V-only DRAMs with trace lengths kept
to a minimum Therefore the chip can drive four banks each
of 16 or 22 bits or two banks of 32 or 39 bits or one bank of
64 or 72 bits
Less loading will slightly reduce the timing parameters and
more loading will increase the timing parameters according
to the graph of Figure 10 The AC performance parameters
are specified with the typical load capacitance of 88
DRAMs This graph can be used to extrapolate the varia-
tions expected with other loading
Because of distributed trace capacitance and inductance
and DRAM input capacitance current spikes can be creat-
ed causing overshoots and undershoots at the DRAM in-
puts that can change the contents of the DRAMs or even
destroy them To remove these spikes a damping resistor
(low inductance carbon) can be inserted between the
DP8409A driver outputs and the DRAMs as close as possi-
ble to the DP8409A The values of the damping resistors
may differ between the different control outputs RASs
CAS Q’s and WE The damping resistors should be deter-
mined by the first prototypes (not wire-wrapped due to the
larger distributed capacitance and inductance) The best
values for the damping resistors are the critical values giving
a critically damped transition on the control outputs Typical
values for the damping resistors will be between 15
100
information see AN-305 ‘‘Precautions to Take When Driv-
ing Memories ’’ )
Hidden Refresh
the lower the loading the higher the value (For more
RF I O
RF I O
RF I O
RF I O
All RAS Active
Active RAS Defined by Table II
Active RAS Defined by Table II
Active RAS Defined by Table II
See Table III for Mode 7
e
e
e
e
EOC
Refresh Request (RFRQ)
EOC
EOC All RAS Active
Conditions
and