DP8409AN-2 National Semiconductor, DP8409AN-2 Datasheet - Page 21

• Manufacturer Part Number: DP8409AN-2
• Description: IC CONTROLLER DYNAMIC RAM 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8409AN-2

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 250mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8409AN-2

Applications
If external control is preferred the DP8409A may be used in
Mode 0 or 4 as in Figure 6
If basic auto access and refresh are required then in cases
where the user requires the minimum of external complexity
Modes 1 and 5 are ideal as shown in Figure 13a The
DP843X2 is used to provide proper arbitration between
memory access and refresh This chip supplies all the nec-
essary control signals to the processor as well as the
DP8409A Furthermore two separate CAS outputs are also
included for systems using byte-writing The refresh clock
RFCK may be divided down from either RGCK using an IC
counter such as the DM74LS393 or better still
DP84300 Programmable Refresh Timer The DP84300 can
provide RFCK periods ranging from 15 4
based on the input clock of 2 to 10 MHz Figure 13b shows
the general timing diagram for interfacing the DP8409A to
different microprocessors using the interface controller
DP843X2
FIGURE 11 Output Load Circuit
FIGURE 13a Connecting the DP8409A Between the 16-Bit Microprocessor and Memory
s to 15 6
TL F 8409 – 21
the
s
21
If the system is complex requiring automatic access and
refresh burst refresh and all-banks auto-write then more
circuitry is required to select the mode This may be accom-
plished by utilizing a PAL
as an address comparator so that when the desired port
address occurs (programmed in the PAL) the comparator
gates the data into a latch where it is connected to the
mode pins of the DP8409A Hence the mode of the
DP8409A can be changed as desired with one PAL chip
merely by addressing the PAL location and then outputting
data to the mode-control pins In this manner all the auto-
matic modes may be selected assigning R C as RFCK al-
ways and CASIN as RGCK always The output from RF I O
may be used as End-of-Count to an interrupt or Refresh
Request to HOLD or BUS REQUEST A complex system
may use Modes 5 and 1 for automatic access and refresh
Modes 3a and 7 for system initialization and Mode 2 (auto-
burst refresh) before and after DMA
FIGURE 12 Waveform
The PAL has two functions One
TL F 8409 – 22
TL F 8409 – 23