DP8390DN National Semiconductor, DP8390DN Datasheet - Page 22

• Manufacturer Part Number: DP8390DN
• Description: IC NIC (NETWORK INT CTRL)48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8390DN

• Controller Type: Network Interface Controller (NIC)
• Voltage - Supply: 5V
• Current - Supply: 40mA
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Operating Temperature: -
• Interface: -
• Other names: *DP8390DN

10 0 Internal Registers
10 3 Register Descriptions (Continued)
DATA CONFIGURATION REGISTER (DCR)
This Register is used to program the NIC for 8- or 16-bit memory interface select byte ordering in 16-bit applications and
establish FIFO threshholds The DCR must be initialized prior to loading the Remote Byte Count Registers LAS is set on
power up
D5 D6
Bit
D0
D1
D2
D3
D4
FT0 FT1
Symbol
WTS
BOS
LAS
AR
LS
WORD TRANSFER SELECT
0 Selects byte-wide DMA transfers
1 Selects word-wide DMA transfers
Note When word-wide mode is selected up to 32k words are addressable A0 remains low
BYTE ORDER SELECT
0 MS byte placed on AD15–AD8 and LS byte on AD7– AD0 (32000 8086)
1 MS byte placed on AD7–AD0 and LS byte on AD15– AD8 (68000)
LONG ADDRESS SELECT
0 Dual 16-bit DMA mode
1 Single 32-bit DMA mode
LOOPBACK SELECT
0 Loopback mode selected Bits D1 D2 of the TCR must also be programmed for Loopback
operation
1 Normal Operation
AUTO-INITIALIZE REMOTE
0 Send Command not executed all packets removed from Buffer Ring under program control
1 Send Command executed Remote DMA auto-initialized to remove packets from Buffer Ring
Note Send Command cannot be used with 68000 type processors
FIFO THRESHHOLD SELECT Encoded FIFO threshhold Establishes point at which bus is
requested when filling or emptying the FIFO During reception the FIFO threshold indicates the
number of bytes (or words) the FIFO has filled serially from the network before bus request
(BREQ) is asserted
Note FIFO threshold setting determines the DMA burst length
FT1
During transmission the FIFO threshold indicates the numer of bytes (or words) the FIFO has
filled from the Local DMA before BREQ is asserted Thus the transmission threshold is 16 bytes
less the receive threshold
0
0
1
1
WTS establishes byte or word transfers
Ignored when WTS is low
When LAS is high the contents of the Remote DMA registers RSAR0 1 are issued as A16– A31
Power up high
for both Remote and Local DMA transfers
RECEIVE THRESHOLDS
7
(Continued)
FT0
0
1
0
1
FT1
6
0EH (WRITE)
FT0
Word Wide
5
2 Words
4 Words
6 Words
1 Word
ARM
4
22
LS
3
Byte Wide
2 Bytes
4 Bytes
8 Bytes
12 Bytes
Description
LAS
2
BOS
1
WTS
0