DP83257VF National Semiconductor, DP83257VF Datasheet - Page 71

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

Bit
D0
D1
D2
D3
D4
D5
D6
D7
5 0 Registers
5 27 INTERRUPT CONDITION COMPARISON REGISTER (ICCR)
The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER
device before it can be written to by the Control Bus Interface
The current state of the Interrupt Condition Register (ICR) is automatically written into the Interrupt Condition Comparison
Register (i e ICCR
During a Control Bus Interface write cycle the PLAYER
Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within ICR when the value of a bit in ICR differs from the
value of the corresponding bit in the interrupt Condition Comparison Register
ACCESS RULES
UDIC
Symbol
DPEC
CPEC
CCRC
CWIC
LEMTC
RCAC
RCBC
UDIC
D7
ADDRESS
1Ah
PHY REQUEST DATA PARITY ERROR COMPARISON The comparison bit for the PHY Request Data Parity
Error bit (DPE) of the Interrupt Condition Register (ICR)
CONTROL BUS DATA PARITY ERROR COMPARISON The comparison bit for the Control Bus Data Parity Error
bit (CPE) of the Interrupt Condition Register (ICR)
CONTROL BUS WRITE COMMAND REJECT COMPARISON The comparison bit for the Control Bus Write
Command Reject bit (CCR) of the Interrupt Condition Register (ICR)
CONDITIONAL WRITE INHIBIT COMPARISON The comparison bit for the Conditional Write Inhibit bit (CWI) of
the Interrupt Condition Register (ICR)
LINK ERROR MONITOR THRESHOLD COMPARISON The comparison bit for the Link Error Monitor Threshold
bit (LEMT) of the Interrupt Condition Register (ICR)
RECEIVE CONDITION A COMPARISON The comparison bit for the Receive Condition A bit (RCA) of the
Interrupt Condition Register (ICR)
RECEIVE CONDITION B COMPARISON The comparison bit for the Receive Condition B bit (RCB) of the
Interrupt Condition Register (ICR)
USER DEFINABLE INTERRUPT COMPARISON The comparison bit for the User Definable Interrupt bit (UDIC) of
the Interrupt Condition Register (ICR)
RCBC
D6
e
ICR) during a Control Bus Interface read-cycle of ICR
(Continued)
Always
READ
RCAC
D5
LEMTC
D4
WRITE
Always
a
CWIC
device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
D3
71
Description
CCRC
D2
CPEC
D1
DPEC
D0
a