DP83257VF National Semiconductor, DP83257VF Datasheet - Page 104

• Manufacturer Part Number: DP83257VF
• Description: IC FDDI LAYER CTRLR 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83257VF

• Controller Type: physical layer controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Interface: -
• Other names: *DP83257VF

Symbol
AIP
AIC
AID7
AID6
AID5
AID4
AID3
AID2
AID1
AID0
ARP
ARC
ARD7
ARD6
ARD5
ARD4
ARD3
ARD2
ARD1
ARD0
BIP
BIC
BID7
BID6
BID5
BID4
BID3
BID2
BID1
BID0
BRP
BRC
6 0 Signal Descriptions
PHY PORT INTERFACE
The PHY Port Interface consists of I O signals used to connect the PLAYER
sublayer or other PLAYER
from one PHY Port Interface and the B Request and B Indicate paths from the second PHY Port Interface Each path
consists of an odd parity bit a control bit and two 4-bit symbols
Refer to section 3 3 the Configuration Switch for more information
Pin
114
112
110
108
106
102
100
115
113
10
12
14
18
20
22
24
26
11
13
15
19
21
23
25
27
98
96
94
6
8
7
9
I O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
PHY Port A Indicate Parity A TTL output signal representing odd parity for the 10-bit wide Port A
Indicate signals (AIP AIC and AID
PHY Port A Indicate Control A TTL output signal indicating that the two 4-bit symbols (AID
AID
PHY Port A Indicate Data TTL output signals representing the first 4-bit data control symbol
AID7 is the most significant bit and AID4 is the least significant bit of the first symbol
PHY Port A Indicate Data TTL output signals representing the second 4-bit data control symbol
AID3 is the most significant bit and AID0 is the least significant bit of the second symbol
PHY Port A Request Parity A TTL input signal representing odd parity for the 10-bit wide Port A
Request signals (ARP ARC and ARD
PHY Port A Request Control A TTL input signal indicating that the two 4-bit symbols
(ARD
PHY Port A Request Data TTL input signals representing the first 4-bit data control symbol
ARD7 is the most significant bit and ARD4 is the least significant bit of the first symbol
PHY Port A Request Data TTL input signals representing the second 4-bit data control symbol
ARD3 is the most significant bit and ARD0 is the least significant bit of the second symbol
PHY Port B Indicate Parity A TTL output signal representing odd parity for the 10-bit wide Port A
Indicate signals (BIP BIC and BID
PHY Port B Indicate Control A TTL output signal indicating that the two 4-bit symbols (BID
BID
PHY Port B Indicate Data TTL output signals representing the first 4-bit data control symbol
BID7 is the most significant bit and BID4 is the least significant bit of the first symbol
PHY Port B Indicate Data TTL output signals representing the second 4-bit data control symbol
BID3 is the most significant bit and BID0 is the least significant bit of the second symbol
PHY Port B Request Parity A TTL input signal representing odd parity for the 10-bit wide Port A
Request signals (BRP BRC and BRD
PHY Port B Request Control A TTL input signal indicating that the two 4-bit symbols
(BRD
a
k
k
device The DP83257 Device has two PHY Port Interfaces The A Request and A Indicate paths
k
k
3 0
3 0
7 4
7 4
l
l
l
l
) are either control symbols (AIC
) are either control symbols (BIC
and ARD
and BRD
(Continued)
k
k
3 0
3 0
l
l
) are either control symbols (ARC
) are either control symbols (BRC
k
k
7 0
7 0
104
k
k
l
l
7 0
7 0
)
)
e
l
e
l
)
)
1) or data symbols (AIC
1) or data symbols (BIC
Description
a
device to the Media Access Control (MAC)
e
e
1) or data symbols (ARC
1) or data symbols (BRC
e
e
0)
0)
e
e
k
0)
k
0)
7 4
7 4
l
l
and
and