CY7C68034-56BAXC Cypress Semiconductor Corp, CY7C68034-56BAXC Datasheet - Page 17

• Manufacturer Part Number: CY7C68034-56BAXC
• Description: IC USB NX2LP NAND CNTRLR 56VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68034-56BAXC

• Controller Type: USB 2.0 NAND Flash Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 43mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• For Use With: CY3686 - DEV KIT USB 2.0 PER OLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 001-04247 Rev. *D
Table 8. NX2LP-Flex Pin Descriptions (continued)
Number
56 QFN
Power and Ground
Pin
46
47
48
49
50
51
52
10
17
27
32
43
55
12
26
28
41
53
56
11
3
7
6
Default Pin
PD1 or
FD[9]
PD2 or
FD[10]
PD3 or
FD[11]
PD4 or
FD[12]
PD5 or
FD[13]
PD6 or
FD[14]
PD7 or
FD[15]
AVCC
AGND
VCC
GND
Name
CE2# or GPIO2
CE3# or GPIO3
CE4# or GPIO4
CE5# or GPIO5
CE6# or GPIO6
CE7# or GPIO7
Firmware
Usage
NAND
CE1#
N/A
N/A
N/A
N/A
Ground
Ground
Power
Power
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Pin
Default
(PD1)
(PD2)
(PD3)
(PD4)
(PD5)
(PD6)
(PD7)
State
[6]
N/A
N/A
N/A
N/A
I
I
I
I
I
I
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
CE1# is a NAND chip enable output signal.
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
CE2# is a NAND chip enable output signal.
GPIO2 is a general purpose I/O signal.
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
CE3# is a NAND chip enable output signal.
GPIO3 is a general purpose I/O signal.
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
CE4# is a NAND chip enable output signal.
GPIO4 is a general purpose I/O signal.
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
CE5# is a NAND chip enable output signal.
GPIO5 is a general purpose I/O signal.
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
CE6# is a NAND chip enable output signal.
GPIO6 is a general purpose I/O signal.
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
CE7# is a NAND chip enable output signal.
GPIO7 is a general purpose I/O signal.
Analog V
provides power to the analog section of the chip.
Analog Ground. Connect to ground with as short a path as
possible.
V
Ground.
CC
. Connect to 3.3V power source.
CC
. Connect this pin to 3.3V power source. This signal
CY7C68033/CY7C68034
Description
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