CY7C63913-PXC Cypress Semiconductor Corp, CY7C63913-PXC Datasheet - Page 33

• Manufacturer Part Number: CY7C63913-PXC
• Description: IC USB PERIPHERAL CTRLR 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63913-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Document 38-08035 Rev. *E
14.2.19 P1.4 – P1.6 Configuration (SCLK, SMOSI, SMISO)
Table 14-15. P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]
14.2.20 P1.7 Configuration
Table 14-16. P1.7 Configuration (P17CR) [0x14] [R/W]
14.2.21 P2 Configuration
Table 14-17. P2 Configuration (P2CR) [0x15] [R/W]
14.2.22 P3 Configuration
Table 14-18. P3 Configuration (P3CR) [0x16] [R/W]
These registers control the operation of pins P1.4–P1.6, respectively. These registers exist in all enCoRe II parts
The P1.4–P1.6 GPIO’s threshold is always set to TTL
When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by
the SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable
bit and the corresponding bit in the P1 data register.
Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3V Drive, High Sink, Open Drain,
and Pull-up Enable control the behavior of the pin
The 50-mA sink drive capability is only available in the CY7C638xx. In the CY7C639xx, only 8-mA sink drive capability is available
on this pin regardless of the setting of the High Sink bit
Bit 7: SPI Use
0 = Disable the SPI alternate function. The pin is used as a GPIO
1 = Enable the SPI function. The SPI circuitry controls the output of the pin
Important Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 15-2):
When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input/output direction of
pins P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically
set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode,
pin P1.4 must be configured as an input.
This register controls the operation of pin P1.7. This register only exists in CY7C638xx and CY7C639xx
The 50-mA sink drive capability is only available in the CY7C638xx. In the CY7C639xx, only 8-mA sink drive capability is available
on this pin regardless of the setting of the High Sink bit
The P1.7 GPIO’s threshold is always set to TTL
This register only exists in CY7C638xx and CY7C639xx. In CY7C638xx this register controls the operation of pins P2.0–P2.1.
In the CY7C639xx, this register controls the operation of pins P2.0–P2.7
The 50-mA sink drive capability is only available on pin P2.7 and only on the CY7C639xx. In the CY7C638xx, only 8-mA sink
drive capability is available on this pin regardless of the setting of the High Sink bit
Read/Write
Read/Write
Read/Write
Read/Write
Default
Default
Default
Default
Field
Field
Field
Field
Bit #
Bit #
Bit #
Bit #
Reserved
Reserved
Reserved
SPI Use
R/W
7
0
7
–
0
7
–
0
7
–
0
Int Enable
Int Enable
Int Enable
Int Enable
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
Int Act Low
Int Act Low
Int Act Low
Int Act Low
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
TTL Thresh
TTL Thresh
TTL Thresh
3.3V Drive
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
High Sink
High Sink
High Sink
High Sink
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
Open Drain
Open Drain
Open Drain
Open Drain
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
Pull-up Enable
Pull-up Enable
Pull-up Enable
Pull-up Enable
R/W
R/W
R/W
R/W
1
0
1
1
1
0
1
1
CY7C63310
CY7C638xx
CY7C639xx
Page 33 of 68
Output Enable
Output Enable
Output Enable
Output Enable
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0