CY7C63913-PXC Cypress Semiconductor Corp, CY7C63913-PXC Datasheet - Page 23

• Manufacturer Part Number: CY7C63913-PXC
• Description: IC USB PERIPHERAL CTRLR 40-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C63913-PXC

• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: MDIP
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Document 38-08035 Rev. *E
10.1.9
Table 10-8. Clock I/O Config (CLKIOCR) [0x32] [R/W]
10.2
When the CPU enters sleep mode the CPUCLK Select (Bit 1,
Table 10-4) is forced to the Internal Oscillator, and the oscil-
lator is stopped. When the CPU comes out of sleep mode it is
running on the internal oscillator. The internal oscillator
recovery time is three clock cycles of the Internal 32-KHz Low-
power Oscillator.
If the system requires the CPU to run off the external clock
after awaking from sleep mode, firmware will need to switch
the clock source for the CPU. If the external clock source is the
external oscillator and the oscillator is disabled, firmware will
need to enable the external oscillator, wait for it to stabilize,
and then change the clock source.
Bit [7:5]: Reserved
Bit 4: XOSC Select
This bit when set, selects the external crystal oscillator clock as clock source of external clock. Care needs to be taken while
selecting the crystal oscillator clock. First enable the crystal oscillator and wait for few cycles, which is oscillator stabilization
period. Then select the crystal clock as clock source. Similarly, while deselect crystal clock, first deselect crystal clock as clock
source then disable the crystal oscillator.
0 = Not select external crystal oscillator clock
1 = Select the external crystal oscillator clock
Bit 3: XOSC Enable
This bit when set enables the external crystal oscillator. The external crystal oscillator shares pads CLKIN and CLKOUT with
two GPIOs—P0.0 and P0.1, respectively. When the external crystal oscillator is enabled, the CLKIN signal comes from the
external crystal oscillator block and the output enables on the GPIOs for P0.0 and P0.1 are disabled, eliminating the possibility
of contention. When the external crystal oscillator is disabled the source for CLKIN signal comes from the P0.0 GPIO input.
0 = Disable the external oscillator
1 = Enable the external oscillator
Note: The external crystal oscillator startup time takes up to 2 ms.
Bit 2: EFTB Disabled
This bit is only available on the CY7C639xx
0 = Enable the EFTB filter
1 = Disable the EFTB filter, causing CLKIN to bypass the EFTB filter
Bit [1:0]: CLKOUT Select
0 0 = Internal 24-MHz Oscillator
0 1 = External crystal oscillator – external crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled,
CLKIN input if the external oscillator is disabled
1 0 = Internal 32-KHz Low-power Oscillator
1 1 = CPUCLK
Read/Write
Default
Field
Bit #
Clock In / Clock Out Configuration
CPU Clock During Sleep Mode
7
–
0
Reserved
6
–
0
5
–
0
XOSC
Select
R/W
4
0
11.0
The microcontroller supports two types of resets: Power-on
Reset (POR) and Watchdog Reset (WDR). When reset is
initiated, all registers are restored to their default states and all
interrupts are disabled.
The occurrence of a reset is recorded in the System Status and
Control Register (CPU_SCR). Bits within this register record
the occurrence of POR and WDR Reset respectively. The
firmware can interrogate these bits to determine the cause of
a reset.
The microcontroller resumes execution from Flash address
0x0000 after a reset. The internal clocking mode is active after
a reset, until changed by user firmware.
Note: The CPU clock defaults to 3 MHz (Internal 24-MHz
Oscillator divide-by-8 mode) at POR to guarantee operation at
the low V
Enable
XOSC
CC
Reset
R/W
3
0
that might be present during the supply ramp.
Disabled
EFTB
R/W
2
0
R/W
1
0
CY7C63310
CY7C638xx
CY7C639xx
CLKOUT Select
Page 23 of 68
R/W
0
0