CY7C68300A-56PVXC Cypress Semiconductor Corp, CY7C68300A-56PVXC Datasheet - Page 4

• Manufacturer Part Number: CY7C68300A-56PVXC
• Description: IC USB 2.0 BRIDGE BULK 56SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C68300A-56PVXC

• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions (continued)
Document #: 38-08031 Rev. *C
SSOP
Pin
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
QFN
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
4
5
6
7
8
9
RESERVE
Pin Name
XTALOUT
DIOW#
DMACK#
DMINUS
XTALIN
DPLUS
PU10K
DIOR#
INTRQ
AGND
CS0#
CS1#
GND
GND
GND
GND
SCL
SDA
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DA0
DA1
DA2
V
V
V
V
V
D
CC
CC
CC
CC
CC
[2]
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
PWR
PWR
PWR
PWR
PWR
Type
GND
GND
GND
GND
GND
Xtal
Xtal
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
O
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Pulled high when Reset is
active. When Reset is
released, the pull-up is
controlled by pin 46(SSOP)/
39(QFN). When VBUS_
PWR_VALID is high, the line
is pulled up. VBUS_PWR
_VALID is polled at start-up
and then every 20 ms.
SCL/SDA will be active for
several ms at start-up. Then
driven high.
Driven high (CMOS)
Driven high (CMOS)
Driven high (CMOS)
Input
Driven high after 2 ms delay ATA Address.
Driven high after 2 ms delay ATA Address.
Driven high after 2 ms delay ATA Address.
Driven high after 2 ms delay ATA Chip Select.
Driven high after 2 ms delay ATA Chip Select.
Default State at Start-up
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Xtal
Xtal
24-MHz Crystal Output (see section 3.2.3).
24-MHz Crystal Input (see section 3.2.3).
Analog Ground. Connect to ground with as short a path as
possible.
V
USB D+ Signal (see section 3.2.1).
USB D- Signal (see section 3.2.1).
Ground.
V
Ground.
Tied to 10k ± 5% pull-up resistor.
Reserved. Tie to GND.
Clock signal for I
3.2.2).
Data signal for I
V
ATA Data bit 0.
ATA Data bit 1.
ATA Data bit 2.
ATA Data bit 3.
ATA Data bit 4.
ATA Data bit 5.
ATA Data bit 6.
ATA Data bit 7.
Ground.
V
Ground.
ATA Control.
ATA Control.
ATA Control.
V
IDE ATA Interrupt request.
CC
CC
CC
CC
CC
. Connect to 3.3V power source.
. Connect to 3.3V power source.
. Connect to 3.3V power source.
. Connect to 3.3V power source.
. Connect to 3.3V power source.
2
C-compatible interface (see section 3.2.2).
2
C-compatible interface (see section
Pin Description
CY7C68300A
Page 4 of 21