ISP1581BD ST-Ericsson Inc, ISP1581BD Datasheet - Page 35

• Manufacturer Part Number: ISP1581BD
• Description: IC USB PERIPHERAL CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1581BD

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 130mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1172; ISP1581BD,557

Philips Semiconductors
9397 750 13462
Product data
Table 34:
Bit
15
14
13
12 to 11 DMA_MODE[1:0]
10 to 8
7
6 to 4
[1]
Symbol
-
IGNORE_IORDY
ATA_MODE
PIO_MODE[2:0]
DIS_XFER_CNT
BURST[2:0]
DMA Configuration register: bit description
Rev. 06 — 23 December 2004
[4]
Description
reserved
A logic 1 ignores the IORDY input signal (UDMA mode only).
A logic 1 configures the DMA core for ATA or MDMA mode.
Used when issuing DMA commands 02H to 07H, 0AH and
0CH; also used when directly accessing task file registers.
A logic 0 configures the DMA core for non-ATA mode. Used
when issuing DMA commands 00H and 01H.
These bits affect the timing for UDMA and MDMA mode:
00H — UDMA/MDMA mode 0: ATA(PI) compatible timings
01H — UDMA/MDMA mode 1: ATA(PI) compatible timings
02H — UDMA/MDMA mode 2: ATA(PI) compatible timings
03H — MDMA mode 3: enables the DMA Strobe Timing
register (see
durations; only used in MDMA mode.
These bits affect the PIO timing (see
00H to 04H — PIO mode 0 to 4: ATA(PI) compatible timings
05H to 07H — reserved.
A logic 1 disables the DMA Transfer Counter (see
The transfer counter can only be disabled in GDMA slave
mode; in master mode the counter is always enabled.
These bits select the DMA burst length and the DREQ timing
(GDMA Slave mode only):
00H — DREQ is asserted until the last byte/word is
transferred or until the FIFO becomes full or empty
01H — DREQ is asserted and negated for each byte/word
transferred
02H — DREQ is asserted and negated for every
2 bytes/words transferred
03H — DREQ is asserted and negated for every
4 bytes/words transferred
04H — DREQ is asserted and negated for every
8 bytes/words transferred
05H — DREQ is asserted and negated for every
12 bytes/words transferred
06H — DREQ is asserted and negated for every
16 bytes/words transferred
07H — DREQ is asserted and negated for every
32 bytes/words transferred
[2][3]
Table 37
Hi-Speed USB peripheral controller
and
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Table
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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38) for non-standard strobe
Table
ISP1581
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Table
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