ISP1581BD ST-Ericsson Inc, ISP1581BD Datasheet - Page 15

• Manufacturer Part Number: ISP1581BD
• Description: IC USB PERIPHERAL CTRLR 64-LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1581BD

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 130mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1172; ISP1581BD,557

Philips Semiconductors
9397 750 13462
Product data
7.8 DMA Interface and DMA Handler
7.9 Power-on reset
The DMA block can be subdivided into two blocks: the DMA Handler and the DMA
Interface.
The firmware writes to the DMA Command register to start a DMA transfer (see
Table
UDMA transfer will start. The Handler interfaces to the same FIFO (internal RAM) as
used by the USB core. Upon receiving the DMA Command, the DMA Handler directs
the data from the internal RAM to the external DMA device or from the external DMA
device to the internal RAM.
The DMA Interface configures the timings and the DMA handshake. Data can be
transferred either using DIOR and DIOW strobes or by the DACK and DREQ
handshakes. The different DMA configurations are set up by writing to the DMA
Configuration register (see
For an IDE-based storage interface, the applicable DMA modes are PIO (Parallel
I/O), MDMA (Multi word DMA; ATA), and UDMA (Ultra DMA; ATA).
For a generic DMA interface, the DMA modes that can be used are Generic DMA
(Slave) and MDMA (Master).
The ISP1581 requires a minimum pulse width of 500 s.
The RESET pin can be either connected to V
externally controlled by the microcontroller, ASIC, and so on. When V
connected to the RESET pin, the internal pulse width t
The power-on reset function can be explained by viewing the dips at t2–t3 and t4–t5
on the V
t0 — The internal POR starts with a HIGH level.
t1 — The detector will see the passing of the trip level and a delay element will add
another t
t2-t3 — The internal POR pulse will be generated whenever V
for more than 11 s.
t4-t5 — The dip is too short (< 11 s) and the internal POR pulse will not react and
will remain LOW.
Fig 3. POR timing.
t0
(1) PORP = power-on reset pulse.
28). The command opcode determines whether a generic DMA, PIO, MDMA or
CC(3.3)
PORP
t1
t
PORP
before it drops to LOW.
curve
Rev. 06 — 23 December 2004
(Figure
Table 33
3).
t2
and
Table
t3
CC(3.3)
t
PORP
34).
Hi-Speed USB peripheral controller
using the internal POR circuit or
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PORP
t4
will be typically 200 ns.
t5
CC(3.3)
004aaa682
ISP1581
drops below V
CC(3.3)
V trip
PORP (1)
V CC(3.3)
is directly
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trip