DS3112N Maxim Integrated Products, DS3112N Datasheet - Page 98
![IC MUX TEMPE T3/E3 IND 256-BGA](/photos/6/82/68222/406-256-bga_sml.jpg)
DS3112N
Manufacturer Part Number
DS3112N
Description
IC MUX TEMPE T3/E3 IND 256-BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3112.pdf
(133 pages)
Specifications of DS3112N
Controller Type
Framer, Multiplexer
Interface
Parallel/Serial
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
150mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
256-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3112N+
Manufacturer:
DALLAS
Quantity:
20 000
10.2 FEAC Status Register Description
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Receive FEAC Codeword Detected (RFCD). This latched read-only event-status bit will be set to a one
each time the FEAC controller has detected and validated a new FEAC codeword. This bit will be cleared when
read and will not be set again until another new codeword is detected. The setting of this bit can cause a hardware
interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will
be allowed to clear when this bit is read.
Bit 1: Receive FEAC Idle (RFI). This latched read-only event status bit will be set to a one each time the FEAC
controller has detected 16 consecutive ones following a valid codeword. This bit will be cleared when read. The
setting of this bit can cause a hardware interrupt to occur if the IERFI bit in the FEAC Control Register (FCR) is
set to one and the FEAC bit in the Interrupt Mask for MSR (IMSR) is set to one.
Bits 8 to 13: Receive FEAC FIFO Data (RFF0 to RFF5). Data from the Receive FEAC FIFO can be read from
these bits. The FEAC codeword is of the form ...0xxxxxx011111111... where the rightmost bit is received first.
These six bits are the debounced and integrated middle six bits of the second byte of the FEAC codeword (i.e., the
six “x” bits). RFF0 is the LSB and is received first while RFF5 is the MSB and is received last.
Bit 14: Receive FEAC FIFO Empty (RFFE). This read-only real time status bit will be set to a one when the
Receive FEAC FIFO is empty and hence the RFF0 to RFF5 bits contain no valid information.
Bit 15: Receive FEAC FIFO Overflow (RFFO). This latched read-only event-status bit will be set to a one when
the receive FEAC controller has attempted to write to an already full Receive FEAC FIFO and current incoming
FEAC codeword is lost. This bit will be cleared when read and will not be set again until another FIFO overflow
occurs (i.e., the Receive FEAC FIFO has been read and then fills beyond capacity).
RFFO
—
—
15
—
7
RFFE
—
—
14
—
6
FSR
FEAC Status Register
92h
RFF5
—
—
13
—
5
98 of 133
RFF4
—
—
12
—
4
RFF3
—
—
11
—
3
RFF2
—
—
10
—
2
RFF1
RFI
—
—
1
9
RFCD
RFF0
—
—
DS3112
0
8