DS21Q43-ATN Maxim Integrated Products, DS21Q43-ATN Datasheet - Page 31

• Manufacturer Part Number: DS21Q43-ATN
• Description: IC FRAMER E1 QUAD 5V 128-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q43-ATN

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 32mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS21Q43A
6.0 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
The DS21Q43A provides for access to both the Sa and the Si bits via three different methods. The first is
via a hardware scheme using the RLINK/RLCLK and TLINK/ TLCLK pins. The first method is
discussed in Section 6.1. The second involves using the internal RAF/RNAF and TAF/TNAF registers
and is discussed in Section 6.2 The third method which is covered in Section 6.3 involves an expanded
version of the second method and is one of the features added to the DS21Q43A from the original
DS2143 definition.
6.1 Hardware Scheme
On the receive side, all of the received data is reported at the RLINK pin. Via RCR2, the user can control
the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can
be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will
identify the Si bits. See Section 11 for detailed timing.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see
Section 6.2 for details) or from the external TLINK pin. Via TCR2, the DS21Q43A can be programmed
to source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits
through the DS21Q43A without them being altered, then the device should be set up to source all 5 Sa
bits via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through
the TSER pin via the clearing of the TCR1.3 bit. Please see the timing diagrams and the transmit data
flow diagram in Section 11 for examples.
6.2 Internal Register Scheme Based on Doubleframe
On the receive side, the RAF and RNAF registers will always report the data as it received in the
Additional and International bit locations. The RAF and RNAF registers are updated with the setting of
the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to
read the RAF and RNAF registers. It has 250 s to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250 s to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if either the DS21Q43A is programmed: (1) to source the Si bits
from the TSER pin, (2) in the CRC4 mode, or (3) to have automatic E-bit insertion enabled. Data in the
Sa bit position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to 1 (please see Section 6.1
for details). Please see the register descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram
in Section 11 for more details.
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