DS2143Q/T&R Maxim Integrated Products, DS2143Q/T&R Datasheet - Page 27

• Manufacturer Part Number: DS2143Q/T&R
• Description: IC CONTROLLER E1 5V LP 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2143Q/T&R

• Controller Type: E1 Controller
• Interface: Parallel/Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RCBR1/RCBR2/RCBR3/RCBR4:
RECEIVE CHANNEL BLOCKING REGISTERS (Address=2B to 2E Hex)
TCBR1/TCBR2/TCBR3/TCBR4:
TRANSMIT CHANNEL BLOCKING REGISTERS (Address=22 to 25 Hex)
10.0 ELASTIC STORE OPERATION
The DS2143 has an onboard two-frame (512 bits) elastic store. This elastic store can be enabled via
RCR2.1. If the elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz
(RCR2.2=0) or 2.048 MHz (RCR2.2=1) clock at the SYSCLK pin. If the elastic store is enabled, then the
user has the option of either providing a frame sync at the RFSYNC pin (RCR1.5=1) or having the
RFSYNC pin provide a pulse on frame or multiframe boundaries (RCR1.5=0). If the user wishes to
obtain pulses at the frame boundary, then RCR1.6 must be set to 0, and if the user wishes to have pulses
occur at the multiframe boundary, then RCR1.6 must be set to 1. If the user selects to apply a 1.544 MHz
clock to the SYSCLK pin, then every fourth channel will be deleted and the F-bit position inserted
(forced to 1). Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will
be deleted. Also, in 1.544 MHz applications, the RCHBLK output will not be active in channels 25
through 32 (or in other words, RCBR4 is not active). See Section 13 for more details. If the 512-bit
elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of
data (256 bits) will be repeated at RSER and the SR1.4 and RIR.3 bits will be set to a 1. If the buffer fills,
then a full frame of data will be deleted and the SR1.4 and RIR.4 bits will be set to a 1.
(MSB)
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
CH8
CH8
SYMBOL
SYMBOL
CH32
CH32
CH1
CH1
CH15
CH23
CH31
CH15
CH23
CH31
CH7
CH7
POSITION
POSITION
CH14
CH22
CH30
RCBR4.7
RCBR1.0
CH14
CH22
CH30
TCBR4.7
TCBR1.0
CH6
CH6
CH13
CH21
CH29
CH13
CH21
CH29
CH5
CH5
NAME AND DESCRIPTION
Receive Channel Blocking Registers.
0 = force the RCHBLK pin to remain low during this channel
time.
1 = force the RCHBLK pin high during this channel time.
NAME AND DESCRIPTION
Receive Channel Blocking Registers.
0 = force the TCHBLK pin to remain low during this channel
time.
1 = force the TCHBLK pin high during this channel time.
CH12
CH20
CH28
CH12
CH20
CH28
CH4
CH4
27 of 44
CH11
CH19
CH27
CH11
CH19
CH27
CH3
CH3
CH18
CH26
CH10
CH18
CH26
CH10
CH2
CH2
CH17
CH25
CH17
CH25
CH1
CH9
CH1
CH9
(LSB)
(LSB)
DS2143/DS2143Q
RCBR1 (2B)
RCBR2 (2C)
RCBR3 (2D)
RCBR4 (2E)
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)