TMC2072-MT SMSC, TMC2072-MT Datasheet - Page 69

• Manufacturer Part Number: TMC2072-MT
• Description: IC CTRLR CIRC 100-TQFP DUAL MODE
• Manufacturer: SMSC
• Series: CircLink™r

Specifications of TMC2072-MT

• Controller Type: I/O Controller
• Interface: Transceiver
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1023

Peripheral Mode CircLink™ Controller
Datasheet
3.2.5
NOTES:
NOTE:
3.2.6
SMSC TMC2072
To preserve the upper and lower bytes of word data in the same packet, COMR4 must be accessed in the order
of 08h access → 09h access.
(access in the order of 09h → 08h, 08h → 08h, or 09h → 09h will not preserve this data).
This restriction is applied for both reading and writing.
The upper/lower relationship is selected by the nSWAP pin.
(1) 16 Bit Mode (W16=H)
(2) 8 Bit Mode and Word Mode=ON (W16=L, WDMD=1)
(3) 8 Bit Mode and Word Mode=Off (W16=L, WDMD=0)
COMR4 Register: Data Register
*1 Not equivalent to the ARCNET original specifications.
- When reading/writing: ARCNET Data register(New)
Writing/ reading out the address in the 1 kByte RAM is indicated by the page register and intra-page
address register. Data access to packet buffer is performed via the data register.
Reading/writing is set by the RDDATA bit of COMR2.
Accessing differently from the setting by RDDATA register will not normally access data. For example, data
register writing with RDDATA = 1 setting, or data register reading with RDDATA = 0 setting will not
normally be performed.
COMR5 Register: Sub-address Register
*1
*1
*1
*1
COMR4
[READ/WRITE]
COMR4
[READ/WRITE]
COMR4
[READ/WRITE]
COMR5
[READ/WRITE]
15-0
15-8
15-8
15-4
7-0
7-0
bit
bit
bit
3-0
bit
(Data Register)
Name
RAMDT15-0
(Data Register)
name
RAMDT15-8
RAMDT7-0
(Data Register)
Name
--------
RAMDT7-0
(Sub-address reg.)
name
--------
SUBAD3-0
DATASHEET
init. Value description
init. Value Description
init. value
init. value
0,0,0,0
X
X
X
X
0
0
Page 69
RAM Data 15-0
Description
RAM Data 15-8
RAM Data 7-0
Reserved (all "0")
RAM Data 7-0
description
reserved (all "0")
Sub Address 3-0
address:08h or 09h
address:08h/09h
address:0Ah
address:08h
Revision 0.1 (06-07-07)