DS2482S-100+T&R Maxim Integrated Products, DS2482S-100+T&R Datasheet - Page 8

• Manufacturer Part Number: DS2482S-100+T&R
• Description: IC I2C TO 1WIRE BRIDGE 8SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS2482S-100+T&R

• Controller Type: I²C Bus Controller
• Interface: I²C
• Voltage - Supply: 3.3 V, 5V
• Current - Supply: 750µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Single-Channel 1-Wire Master
The read-only Status Register is the general means for
the DS2482-100 to report bit-type data from the 1-Wire
side, 1-Wire busy status, and its own reset status to the
host processor. All 1-Wire communication commands
and the Device Reset command position the read
pointer at the Status Register for the host processor to
read with minimal protocol overhead. Status information
is updated during the execution of certain commands
only. Details are given in the description of the various
status bits that follow.
The 1WB bit reports to the host processor whether the
1-Wire line is busy. During 1-Wire communication 1WB
is 1; once the command is completed, 1WB returns to
its default 0. Details on when 1WB changes state and
for how long it remains at 1 are found in the Function
Commands section.
The PPD bit is updated with every 1-Wire Reset com-
mand. If the DS2482-100 detects a presence pulse from
a 1-Wire device at t
cycle, the PPD bit is set to 1. This bit returns to its default
0 if there is no presence pulse or if the 1-Wire line is
shorted during a subsequent 1-Wire Reset command.
The SD bit is updated with every 1-Wire Reset com-
mand. If the DS2482-100 detects a logic 0 on the
1-Wire line at t
SD bit is set to 1. This bit returns to its default 0 with a
subsequent 1-Wire Reset command provided that the
short has been removed. If SD is 1, PPD is 0. The
DS2482-100 cannot distinguish between a short and a
DS1994 or DS2404 signaling a 1-Wire interrupt. For this
reason, if a DS2404 or DS1994 is used in the applica-
tion, the interrupt function must be disabled. The inter-
rupt signaling is explained in the respective 1-Wire
device data sheets.
8
_______________________________________________________________________________________
BIT 7
DIR
SI
during the presence-detect cycle, the
BIT 6
TSB
MSP
Presence-Pulse Detect (PPD)
during the presence-detect
BIT 5
Short Detected (SD)
SBR
Status Register
1-Wire Busy (1WB)
BIT 4
RST
The LL bit reports the logic state of the active 1-Wire
line without initiating any 1-Wire communication. The
1-Wire line is sampled for this purpose every time the
Status Register is read. The sampling and updating of
the LL bit takes place when the host processor has
addressed the DS2482-100 in read mode (during the
acknowledge cycle), provided that the read pointer is
positioned at the Status Register.
If the RST bit is 1, the DS2482-100 has performed an
internal reset cycle, either caused by a power-on reset
or from executing the Device Reset command. The RST
bit is cleared automatically when the DS2482-100 exe-
cutes a Write Configuration command to restore the
selection of the desired 1-Wire features.
The SBR bit reports the logic state of the active 1-Wire line
sampled at t
first bit of a 1-Wire Triplet command. The power-on default
of SBR is 0. If the 1-Wire Single Bit command sends a 0
bit, SBR should be 0. With a 1-Wire Triplet command,
SBR could be 0 as well as 1, depending on the response
of the 1-Wire devices connected. The same result applies
to a 1-Wire Single Bit command that sends a 1 bit.
The TSB bit reports the logic state of the active 1-Wire
line sampled at t
Triplet command. The power-on default of TSB is 0.
This bit is updated only with a 1-Wire Triplet command
and has no function with other commands.
Whenever a 1-Wire Triplet command is executed, this
bit reports to the host processor the search direction
that was chosen by the third bit of the triplet. The
power-on default of DIR is 0. This bit is updated only
with a 1-Wire Triplet command and has no function with
other commands. For additional information, see the
description of the 1-Wire Triplet command and
Application Note 187: 1-Wire Search Algorithm .
BIT 3
LL
MSR
Status Register Bit Assignment
BIT 2
of a 1-Wire Single Bit command or the
SD
MSR
of the second bit of a 1-Wire
Branch Direction Taken (DIR)
Triplet Second Bit (TSB)
Single Bit Result (SBR)
BIT 1
PPD
Device Reset (RST)
Logic Level (LL)
BIT 0
1WB